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Audio Codec for Recordable DVD ADAV803
FEATURES
Stereo analog-to-digital converter (ADC) Supports 48/96 kHz sample rates 102 dB dynamic range Single-ended input Automatic level control Stereo digital-to-analog converter (DAC) Supports 32/44.1/48/96/192 kHz sample rates 101 dB dynamic range Single-ended output Asynchronous operation of ADC and DAC Stereo sample rate converter (SRC) Input/output range: 8 kHz to 192 kHz 140 dB dynamic range Digital interfaces Record Playback Auxiliary record Auxiliary playback S/PDIF (IEC60958) input and output Digital interface receiver (DIR) Digital interface transmitter (DIT) PLL-based audio MCLK generators Generates required DVDR system MCLKs Device control via I2C(R)-compatible serial port 64-lead LQFP package
XOUT XIN
FUNCTIONAL BLOCK DIAGRAM
SYSCLK1 SYSCLK2 SYSCLK3 MCLKO MCLKI SDA SCL AD0 AD1
PLL
CONTROL REGISTERS RECORD DATA OUTPUT OLRCLK OBCLK OSDATA OAUXLRCLK OAUXBCLK OAUXSDATA DIT DITOUT
VINL VINR VREF
ANALOG-TO-DIGITAL CONVERTER REFERENCE SRC DIGITAL INPUT/OUTPUT SWITCHING MATRIX (DATA PATH)
AUX DATA OUTPUT
VOUTL VOUTR
DIGITAL-TO-ANALOG CONVERTER
FILTD PLAYBACK DATA INPUT AUX DATA INPUT ZEROL/INT DIR ZEROR
ADAV803
ISDATA
IAUXSDATA
ILRCLK
IBCLK
IAUXLRCLK
IAUXBCLK
DIRIN
Figure 1.
APPLICATIONS
DVD-recordable All formats CD-R/W
PRODUCT OVERVIEW
The ADAV803 is a stereo audio codec intended for applications such as DVD or CD recorders that require high performance and flexible, cost-effective playback and record functionality. The ADAV803 features Analog Devices' proprietary, high performance converter cores to provide record (ADC), playback (DAC), and format conversion (SRC) on a single chip. The ADAV803 record channel features variable input gain to allow for adjustment of recorded input levels and automatic level control, followed by a high performance stereo ADC whose digital output is sent to the record interface. The record channel also features level detectors that can be used in feedback loops to adjust input levels for optimum recording. The playback channel features a high performance stereo DAC with independent digital volume control. The sample rate converter (SRC) provides high performance sample rate conversion to allow inputs and outputs that require different sample rates to be matched. The SRC input can be selected from playback, auxiliary, DIR, or ADC (record). The SRC output can be applied to the playback DAC, both main and auxiliary record channels, and a DIT. Operation of the ADAV803 is controlled via an I2C-compatible serial interface, which allows the programming of individual control register settings. The ADAV803 operates from a single analog 3.3 V power supply and a digital power supply of 3.3 V with optional digital interface range of 3.0 V to 3.6 V. The part is housed in a 64-lead LQFP package and is characterized for operation over the commercial temperature range of -40C to +85C.
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.326.8703 (c) 2004 Analog Devices, Inc. All rights reserved.
04756-0-001
ADAV803 TABLE OF CONTENTS
Specifications..................................................................................... 3 Test Conditions............................................................................. 3 ADAV803 Specifications ............................................................. 3 Timing Specifications .................................................................. 6 Temperature Range ...................................................................... 7 Absolute Maximum Ratings............................................................ 8 ESD Caution.................................................................................. 8 Pin Configuration and Function Descriptions............................. 9 Typical Performance Characteristics ........................................... 11 Functional Description .................................................................. 15 ADC Section ............................................................................... 15 DAC Section................................................................................ 18 Sample Rate Converter (SRC) Functional Overview ............ 19 PLL Section ................................................................................. 22 SPDIF Transmitter and Receiver.............................................. 23 Serial Data Ports ......................................................................... 27 Interface Control ............................................................................ 30 I2C Interface ................................................................................ 30 Block Reads and Writes ............................................................. 31 Register Descriptions ..................................................................... 32 Layout Considerations................................................................... 55 ADC ............................................................................................. 55 DAC.............................................................................................. 55 PLL ............................................................................................... 55 Reset and Power-Down Considerations ................................. 55 Outline Dimensions ....................................................................... 56 Ordering Guide .......................................................................... 56
REVISION HISTORY
7/04--Revision 0: Initial Version
Rev. 0 | Page 2 of 56
ADAV803 SPECIFICATIONS
TEST CONDITIONS
Test conditions, unless otherwise noted. Table 1.
Test Parameter Supply Voltage Analog Digital Ambient Temperature Master Clock (XIN) Measurement Bandwidth Word Width (All Converters) Load Capacitance on Digital Outputs ADC Input Frequency DAC Output Frequency Digital Input Digital Output Condition 3.3 V 3.3 V 25C 12.288 MHz 20 Hz to 20 kHz 24 bits 100 pF 1007.8125 Hz at -1 dBFS 960.9673 Hz at 0 dBFS Slave Mode, I2S Justified Format Slave Mode, I2S Justified Format
ADAV803 SPECIFICATIONS
Table 2.
Parameter PGA SECTION Input Impedance Minimum Gain Maximum Gain Gain Step REFERENCE SECTION Absolute Voltage, VREF VREF Temperature Coefficient ADC SECTION Number of Channels Resolution Dynamic Range Unweighted A-Weighted Total Harmonic Distortion plus Noise -88 -87 Analog Input Input Range ( Full Scale) DC Accuracy Gain Error Interchannel Gain Mismatch Gain Drift Offset Crosstalk (EIAJ Method) Volume Control Step Size (256 Steps) 1.0 -1.5 -0.8 0.05 1 -10 -110 0.39 dB dB V rms dB dB mdB/C mV dB % per step Min Typ 4 0 24 0.5 1.5 80 2 24 99 98 102 101 Max Unit k dB dB dB V ppm/C Comments
Bits dB dB dB dB -60 dB input fS = 48 kHz fS = 96 kHz fS = 48 kHz fS = 96 kHz Input = -1.0 dBFS fS = 48 kHz fS = 96 kHz
98
Rev. 0 | Page 3 of 56
ADAV803
Parameter Min Maximum Volume Attenuation Mute Attenuation Group Delay fS = 48 kHz fS = 96 kHz ADC LOW-PASS DIGITAL DECIMATION FILTER CHARACTERISTICS1 Pass-Band Frequency Stop-Band Frequency Stop-Band Attenuation Pass-Band Ripple ADC HIGH-PASS DIGITAL FILTER CHARACTERISTICS Cutoff Frequency SRC SECTION Resolution Sample Rate SRC MCLK Maximum Sample Rate Ratios Upsampling Downsampling Dynamic Range Total Harmonic Distortion plus Noise DAC SECTION Number of Channels Resolution Dynamic Range Unweighted A-Weighted Total Harmonic Distorton plus Noise -91 -90 Analog Outputs Output Range ( Full Scale) Output Resistance Common-Mode Output Voltage DC Accuracy Gain Error Interchannel Gain Mismatch Gain Drift DC Offset Crosstalk (EIAJ Method) Phase Deviation Mute Attenuation Volume Control Step Size (256 Steps) 1.0 60 1.5 -2 -0.8 0.05 1
+30
Typ -48 910 460 22 44 26 52 120 120 0.01 0.01 0.9 24
Max
Unit dB dB s s kHz kHz kHz kHz dB dB dB dB Hz Bits kHz MHz
Comments ADC outputs all zero codes
Sample rate: 48 kHz Sample rate: 96 kHz Sample rate: 48 kHz Sample rate: 96 kHz Sample rate: 48 kHz Sample rate: 96 kHz Sample rate: 48 kHz Sample rate: 96 kHz fS = 48 kHz
8 138 x fS-MAX
192 33
XIN = 27 MHz fS-MAX is the greater of the input or output sample rate
1:8 7.75:1 140 120 dB 20 Hz to fS/2, 1 kHz, -60 dBFS input, fIN = 44.1 kHz, fOUT = 48 kHz 20 Hz to fS/2, 1 kHz, 0 dBFS input. fIN = 44.1 kHz, fOUT = 48 kHz
2 24 99 98 101 100
Bits dB dB dB dB dB dB V rms V dB dB mdB/C mV dB Degrees dB dB 20 Hz to 20 kHz, -60 dB input fS = 48 kHz fS = 96 kHz fS = 48 kHz fS = 96 kHz Referenced to 1V rms fS = 48 kHz fS = 96 kHz
97
-30 -110 0.05 -95.625 0.375
Rev. 0 | Page 4 of 56
ADAV803
Parameter Min Group Delay 48 kHz 96 kHz 192 kHz DAC LOW-PASS DIGITAL INTERPOLATION FILTER CHARACTERISTICS Pass-Band Frequency Typ 630 155 66 20 22 42 24 26 60 70 70 70 0.002 0.002 0.005 27/54 27/54 256 256 256 768 768 512 65 75 75 27.2 200 27.2 2.0 200 Max Unit s s s kHz kHz kHz kHz kHz kHz dB dB dB dB dB dB MHz MHz x fS x fS x fS ps rms ps rms ps rms kHz mV kHz V V A A V V pF Sample rate: 44.1 kHz Sample rate: 48 kHz Sample rate: 96 kHz Sample rate: 44.1 kHz Sample rate: 48 kHz Sample rate: 96 kHz Sample rate: 44.1 kHz Sample rate: 48 kHz Sample rate: 96 kHz Sample rate: 44.1 kHz Sample rate: 48 kHz Sample rate: 96 kHz Comments
Stop-Band Frequency
Stop-Band Attenuation
Pass-Band Ripple
PLL SECTION Master Clock Input Frequency Generated System Clocks MCLKO SYSCLK1 SYSCLK2 SYSCLK3 Jitter SYSCLK1 SYSCLK2 SYSCLK3 DIR SECTION Input Sample Frequency Differential Input Voltage DIT SECTION Output Sample Frequency DIGITAL I/O Input Voltage High, VIH Input Voltage Low, VIL Input Leakage, IIH @ VIH = 3.3 V Input Leakage, IIL @ VIL = 0 V Output Voltage High, VOH @ IOH = 0.4 mA Output Voltage Low, VOL @ IOL = -2 mA Input Capacitance POWER Supplies Voltage, AVDD Voltage, DVDD Voltage, ODVDD Operating Current Analog Current Digital Current Digital Interface Current DIRIN/DIROUT Current PLL Current
256/384/512/768 x 32/44.1/ 48 kHz 256/384/512/768 x 32/44.1/ 48 kHz 256/512 x 32/44.1/48 kHz
200 DVDD 0.8 10 10 0.4 15
2.4
3.0 3.0 3.0
3.3 3.3 3.3
3.6 3.6 3.6 60 38 13
V V V All supplies at 3.3 V mA mA mA mA mA
5 18
Rev. 0 | Page 5 of 56
ADAV803
Parameter Power-Down Current Analog Current Digital Current Digital Interface Current DIRIN/DIROUT Current PLL Current Power Supply Rejection Signal at Analog Supply Pins Min Typ 18 2.5 700 3.5 900 -70 -70 Max Unit mA mA A mA A dB dB 1 kHz, 300 mV p-p 20 kHz, 300 mV p-p Comments RESET low, no MCLK
1
Guaranteed by design.
TIMING SPECIFICATIONS
Timing specifications are guaranteed over the full temperature and supply range. Table 3.
Parameter MASTER CLOCK AND RESET fMCLK MCLKI Frequency fXIN XIN Frequency tRESET RESET Low I C PORT fSCL tSCLH tSCLL Start Condition tSCS tSCH tDS tSCR tSCF tSDR tSDF Stop Condition tSCS SERIAL PORTS1 Slave Mode tSBH tSBL fSBF tSLS tSLH tSDS tSDH tSDD
2
Min
Typ 12.288 27
Max 54 54
Unit MHz MHz ns kHz s s s s ns ns ns ns ns s
Comments
20 400 0.6 1.3 0.6 0.6 100 300 300 300 300 0.6
SCL Clock Frequency SCL High SCL Low Setup Time Hold Time Data Setup Time SCL Rise Time SCL Fall Time SDA Rise Time SDA Fall Time Setup Time
Relevant for repeated start condition After this period, the first clock is generated
xBCLK High xBCLK Low xBCLK Frequency xLRCLK Setup xLRCLK Hold xSDATA Setup xSDATA Hold xSDATA Delay
40 40 64 x fS 10 10 10 10 10
ns ns ns ns ns ns ns To xBCLK rising edge From xBCLK rising edge To xBCLK rising edge From xBCLK rising edge From xBCLK falling edge
Rev. 0 | Page 6 of 56
ADAV803
Parameter Master Mode tMLD tMDD tMDS tMDH Min xLRCLK Delay xSDATA Delay xSDATA Setup xSDATA Hold Typ Max 5 10 10 10 Unit ns ns ns ns Comments From xBCLK falling edge From xBCLK falling edge From xBCLK rising edge From xBCLK rising edge
1
The prefix x refers to I-, O-, IAUX-, or OAUX- for the full pin name.
TEMPERATURE RANGE
Table 4.
Parameter Specifications Guaranteed Functionality Guaranteed Storage Min -40 -65 Typ 25 Max +85 +150 Unit C C C
Rev. 0 | Page 7 of 56
ADAV803 ABSOLUTE MAXIMUM RATINGS
Table 5.
Parameter DVDD to DGND and ODVDD to DGND AVDD to AGND Digital Inputs Analog Inputs AGND to DGND Reference Voltage Soldering (10 s) Rating 0 V to 4.6 V 0 V to 4.6 V DGND - 0.3 V to DVDD + 0.3 V AGND - 0.3 V to AVDD + 0.3 V -0.3 V to +0.3 V Indefinite short circuit to ground 300C
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.
Rev. 0 | Page 8 of 56
ADAV803 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
CAPRN
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
VINR 1 VINL 2 AGND 3 AVDD 4 DIR_LF 5 DIR_GND 6 DIR_VDD 7 RESET 8 AD0 9 SDA 10 SCL 11 AD1 12 ZEROL/INT 13 ZEROR 14 DVDD 15 DGND 16
VOUTR
48 ADVDD 47 ADGND 46 PLL_LF2 45 PLL_LF1 44 PLL_GND 43 PLL_VDD 42 DGND 41 SYSCLK1 40 SYSCLK2 39 SYSCLK3 38 XIN 37 XOUT 36 MCLKO 35 MCLKI 34 DVDD 33 DGND
CAPRP
CAPLN
VOUTL IAUXLRCLK
CAPLP
AGND
AGND
AGND
AGND
FILTD
AVDD
AVDD
VREF
NC
PIN 1 INDICATOR
ADAV803
TOP VIEW (Not to Scale)
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
NC IAUXBCLK
OAUXLRCLK
OAUXSDATA
IAUXSDATA
ISDATA
OSDATA
OLRCLK
ODGND
DITOUT
IBCLK
OBCLK
DIRIN
ILRCLK
ODVDD
OAUXBCLK
NC = NO CONNECT
Figure 2. Pin Configuration
Table 6. Pin Function Descriptions
Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 Mnemonic VINR VINL AGND AVDD DIR_LF DIR_GND DIR_VDD RESET AD0 SDA SCL AD1 ZEROL/INT ZEROR DVDD DGND ILRCLK IBCLK ISDATA OLRCLK OBCLK OSDATA DIRIN ODVDD ODGND DITOUT I/O I I Description Analog Audio Input, Right Channel. Analog Audio Input, Left Channel. Analog Ground. Analog Voltage Supply. DIR Phase-Locked Loop (PLL) Filter Pin. Supply Ground for DIR Analog Section. This pin should be connected to AGND. Supply for DIR Analog Section. This pin should be connected to AVDD. Asychronous Reset Input (Active Low). I2C Address LSB. Data Input/Output of I2C-Compatible Control Interface. Clock Input of I2C Compatible Control Interface. I2C Address MSB. Left Channel (Output) Zero Flag or Interrupt (Output) Flag. The function of this pin is determined by the INTRPT pin in DAC Control Register 4. Right Channel (Output) Zero Flag. Digital Voltage Supply. Digital Ground. Sampling Clock (LRCLK) of Playback Digital Input Port. Serial Clock (BCLK) of Playback Digital Input Port. Data Input of Playback Digital Input Port. Sampling Clock (LRCLK) of Record Digital Output Port. Serial Clock (BCLK) of Record Digital Output Port. Data Output of Record Digital Output Port. Input to Digital Input Receiver (S/PDIF). Interface Digital Voltage Supply. Interface Digital Ground. S/PDIF Output from DIT.
Rev. 0 | Page 9 of 56
I I I/O I I O O
I/O I/O I I/O I/O O I
O
04756-0-002
ADAV803
Pin No. 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 Mnemonic OAUXLRCLK OAUXBCLK OAUXSDATA IAUXLRCLK IAUXBCLK IAUXSDATA DGND DVDD MCLKI MCLKO XOUT XIN SYSCLK3 SYSCLK2 SYSCLK1 DGND PLL_VDD PLL_GND PLL_LF1 PLL_LF2 ADGND ADVDD VOUTR NC VOUTL NC AVDD AGND FILTD AGND VREF AGND AVDD CAPRN CAPRP AGND CAPLP CAPLN I/O I/O I/O O I/O I/O I Description Sampling Clock (LRCLK) of Auxiliary Digital Output Port. Serial Clock (BCLK) of Auxiliary Digital Output Port. Data Output of Auxiliary Digital Output Port. Sampling Clock (LRCLK) of Auxiliary Digital Input Port. Serial (BCLK) of Auxiliary Digital Input Port. Data Input of Auxiliary Digital Input Port. Digital Ground. Digital Supply Voltage. External MCLK Input. Oscillator Output. Crystal Input. Crystal or External MCLK Input. System Clock 3 (from PLL2). System Clock 2 (from PLL2). System Clock 1 (from PLL1). Digital Ground. Supply for PLL Analog Section. This pin should be connected to AVDD. Ground for PLL Analog Section. This pin should be connected to AGND. Loop Filter for PLL1. Loop Filter for PLL2. Analog Ground (Mixed Signal). This pin should be connected to AGND. Analog Voltage Supply (Mixed Signal). This pin should be connected to AVDD. Right Channel Analog Output. No Connect. Left Channel Analog Output. No Connect. Analog Voltage Supply. Analog Ground. Output DAC Reference Decoupling. Analog Ground. Voltage Reference Voltage. Analog Ground. Analog Voltage Supply. ADC Modulator Input Filter Capacitor (Right Channel, Negative). ADC Modulator Input Filter Capacitor (Right Channel, Positive). Analog Ground. ADC Modulator Input Filter Capacitor (Left Channel, Positive). ADC Modulator Input Filter Capacitor (Left Channel, Negative).
I O I I O O O
O O
Rev. 0 | Page 10 of 56
ADAV803 TYPICAL PERFORMANCE CHARACTERISTICS
0
0
MAGNITUDE (dB)
-50
MAGNITUDE (dB)
-50
-100
-100
04756-0-003
-150 0 0.5 1.0 1.5 FREQUENCY (Normalized to fS)
-150 0 96 192 FREQUENCY (kHz) 288
2.0
384
Figure 3. ADC Composite Filter Response
Figure 6. DAC Composite Filter Response, 48 kHz
5
0
0
MAGNITUDE (dB)
MAGNITUDE (dB)
-5
-50
-10 -15
-100
-20 -25 -30 0 5 10 FREQUENCY (Hz) 15
04756-0-004 04756-0-007
-150 0 12 24 FREQUENCY (kHz) 36
20
48
Figure 4. ADC High-Pass Filter Response, fS = 48 kHz
Figure 7. DAC Pass-Band Filter Response, 48 kHz
5 0
0.06
0.04
-5
MAGNITUDE (dB) MAGNITUDE (dB)
0.02
-10 -15
0.00
-0.02
-20 -25 -30 0 5 10 FREQUENCY (Hz) 15
04756-0-005
20
-0.06 0 8 16 FREQUENCY (kHz)
24
Figure 5. ADC High-Pass Filter Response, fS = 96 kHz
Figure 8. DAC Filter Ripple, 48 kHz
Rev. 0 | Page 11 of 56
04756-0-008
-0.04
04756-0-006
ADAV803
0 0
-50
MAGNITUDE (dB)
-50
MAGNITUDE (dB)
-100
-100 -150
04756-0-012
04756-0-009
-150 0 192 384 FREQUENCY (kHz) 576
-200 0 384 768 FREQUENCY (kHz) 1152
768
1536
Figure 9. DAC Composite Filter Response, 96 kHz
Figure 12. DAC Composite Filter Response, 192 kHz
0
0
-2
MAGNITUDE (dB)
-50
MAGNITUDE (dB)
04756-0-010
-4
-6
-100
-8
04756-0-013
-150 0 24 48 FREQUENCY (kHz) 72
96
-10 48
64
80 FREQUENCY (kHz)
96
Figure 10. DAC Pass-Band Filter Response, 96 kHz
Figure 13. DAC Pass-Band Filter Response, 192 kHz
0.10
0.50 0.40 0.30
0.05
0.20
MAGNITUDE (dB) MAGNITUDE (dB)
04756-0-011
0.10 0.00 -0.10 -0.20
0.00
-0.05
-0.30 -0.40 -0.50 0 8 16 32 FREQUENCY (kHz) 64
04756-0-014
-0.10 0 24 48 FREQUENCY (kHz) 72
96
Figure 11. DAC Filter Ripple, 96 kHz
Figure 14. DAC Filter Ripple, 192 kHz
Rev. 0 | Page 12 of 56
ADAV803
0 -20 -40
MAGNITUDE (dB)
0 DNR = 102dB (A-Weighted) -20 -40
MAGNITUDE (dB)
THD+N = 95dB
-60 -80 -100 -120
04756-0-015
-60 -80 -100 -120 -140 -160 0 5 10 15 20 25 30 FREQUENCY (kHz) 35 40
04756-0-018
-140 -160 0 2 4 6 8 10 12 14 FREQUENCY (kHz) 16 18
20
45 48
Figure 15. DAC Dynamic Range, fS = 48 kHz
Figure 18. DAC THD + N, fS = 96 kHz
0 -20 -40
MAGNITUDE (dB)
0 THD+N = 96dB -20 -40
MAGNITUDE (dB)
DNR = 102dB (A-Weighted)
-60 -80 -100 -120
04756-0-016
-60 -80 -100 -120 -140 -160 0 5 10 FREQUENCY (kHz) 15
04756-0-019
-140 -160 0 2 4 6 8 10 12 14 FREQUENCY (kHz) 16 18
20
20
Figure 16. DAC THD + N, fS = 48 kHz
Figure 19. ADC Dynamic Range, fS = 48 kHz
0 -20 -40
MAGNITUDE (dB)
0 DNR = 102dB (A-Weighted) -20 -40
MAGNITUDE (dB)
THD+N = 92dB (VIN = -3dB)
-60 -80 -100 -120
04756-0-017
-60 -80 -100 -120 -140 -160 0 5 10 FREQUENCY (kHz) 15
04756-0-020
-140 -160 0 5 10 15 20 25 30 FREQUENCY (kHz) 35 40
45 48
20
Figure 17. DAC Dynamic Range, fS = 96 kHz
Figure 20. DAC THD + N, fS = 48 kHz
Rev. 0 | Page 13 of 56
ADAV803
0 -20 -40
MAGNITUDE (dB)
0 DNR = 102dB (A-Weighted) -20 -40
MAGNITUDE (dB)
THD+N = 92dB (VIN = -3dB)
-60 -80 -100 -120
04756-0-021
-60 -80 -100 -120 -140 -160 0 8 16 24 32 FREQUENCY (kHz) 40
04756-0-022
-140 -160 0 8 16 24 32 FREQUENCY (kHz) 40
48
48
Figure 21. ADC Dynamic Range, fS = 96 kHz
Figure 22. ADC THD + N, fS = 96 kHz
Rev. 0 | Page 14 of 56
ADAV803 FUNCTIONAL DESCRIPTION
ADC SECTION
The ADAV803's ADC section is implemented using a secondorder multibit (5 bits) - modulator. The modulator is sampled at either half of the ADC MCLK rate (modulator clock = 128 x fS) or one-quarter of the ADC MCLK rate (modulator clock = 64 x fS). The digital decimator consists of a Sinc^5 filter followed by a cascade of three half-band FIR filters. The Sinc decimates by a factor of 16 at 48 kHz and by a factor of 8 at 96 kHz. Each of the half-band filters decimates by a factor of 2. Figure 23 shows the details of the ADC section. The ADC can be clocked by a number of different clock sources to control the sample rate. MCLK selection for the ADC is set by Internal Clocking Control Register 1 (Address 0x76). The ADC provides an output word of up to 24 bits of resolution in twos complement format. The output word can be routed to either the output ports, the sample rate converter, or the SPDIF digital transmitter.
DIR PLL(256 x fS) DIR PLL(512 x fS) PLL2 INTERNAL
ADC
04756-0-023
Programmable Gain Amplifier (PGA)
The input of the record channel features a PGA that converts the single-ended signal to a differential signal, which is applied to the analog - modulator of the ADC. The PGA can be programmed to amplify a signal by up to 24 dB in 0.5 dB increments. Figure 24 shows the structure of the PGA circuit.
4k TO 64k EXTERNAL CAPACITOR (1nF NPO) 125
4k VREF
CAPxN EXTERNAL TO CAPACITOR MODULATOR (1nF NPO)
04756-0-024 04756-0-025
125 8k 8k EXTERNAL CAPACITOR (1nF NPO)
CAPxP
Figure 24. PGA Block Diagram
Analog - Modulator
The ADC features a second-order, multibit, - modulator. The input features two integrators in cascade followed by a flash converter. This multibit output is directed to a scrambler, followed by a DAC for loop feedback. The flash ADC output is also converted from thermometer coding to binary coding for input as a 5-bit word to the decimator. Figure 25 shows the ADC block diagram. The ADC also features independent digital volume control for the left and right channels. The volume control consists of 256 linear steps, with each step reducing the digital output codes by 0.39%. Each channel also has a peak detector that records the peak level of the input signal. The peak detector register is cleared by reading it.
ADC MCLK DIVIDER
ADC MCLK
Figure 23. Clock Path Control on the ADC
MULTI-BIT - MODULATOR
PLL1 INTERNAL
MCLKI
REG 0x6F BITS 1-0
XIN
REG 0x76 BITS 4-2
DECIMATOR VOLUME CONTROL
HPF
PEAK DETECT
ADC MODCLK SINC^5 ADC MCLK/2 (TYP 6.144MHz)
384kHz 768kHz
HALF-BAND 192kHz FILTER 384kHz
96kHz SINC COMPENSATION 192kHz
HALF-BAND 48kHz FILTER 96kHz
Figure 25. ADC Block Diagram
Rev. 0 | Page 15 of 56
ADAV803
Automatic Level Control (ALC)
The ADC record channel features a programmable automatic level control block. This block monitors the level of the ADC output signal and automatically reduces the gain, if the signal at the input pins causes the ADC output to exceed a preset limit. This function can be useful to maximize the signal dynamic range when the input level is not well defined. The PGA can be used to amplify the unknown signal, and the ALC reduces the gain until the ADC output is within the preset limits. This results in maximum front end gain. Because the ALC block monitors the output of the ADC, the volume control function should not be used. The ADC volume control scales the results from the ADC, and any distortion caused by the input signal exceeding the input range of the ADC is still present at the output of the ADC, but scaled by a value determined by the volume control register. The ALC block has two functions, attack mode and recovery mode. Recovery mode consists of three settings: no recovery, normal recovery, and limited recovery. These modes are discussed in the following sections. Figure 26 is a flow diagram of the ALC block. When the ALC has been enabled, any changes made to the PGA or ALC settings are ignored. To change the functionality of the ALC, it must first be disabled. The settings can then be changed and the ALC re-enabled.
No Recovery Mode
By default, there is no gain recovery. Once the gain has been reduced, it is not recovered until the ALC has been reset, either by toggling the ALCEN bit in ALC Control Register 1 or by writing any value to ALC Control Register 3. The latter option is more efficient, because it requires only one write operation to reset the ALC function. No recovery mode prevents volume modulation of the signal caused by adjusting the gain, which can create undesirable artifacts in the signal. The gain can be reduced but not recovered. Therefore, care should be taken that spurious signals do not interfere with the input signal, because these might trigger a gain reduction unnecessarily.
Normal Recovery Mode
Normal recovery mode allows for the PGA gain to be recovered, provided that the input signal meets certain criteria. First, the ALC must not be in attack mode, that is, the PGA gain has been reduced sufficiently such that the input signal is below the level set by the attack threshold bits. Second, the output result from the ADC must be below the level set by the recovery threshold bits in the ALC control register. If both of these criteria are met, the gain is recovered by one step (0.5 dB). The gain is incrementally restored to its original value, assuming that the ADC output level is below the recovery threshold at intervals determined by the recovery time bits. If the ADC output level exceeds the recovery threshold while the PGA gain is being restored, the PGA gain value is held and does not continue restoration until the ADC output level is again below the recovery threshold. Once the PGA gain is restored to its original value, it is not changed again unless the ADC output value exceeds the attack threshold and the ALC then enters attack mode. Care should be taken when using this mode to choose values for the attack and recovery thresholds that prevent excessive volume modulation caused by continuous gain adjustments.
Attack Mode
When the absolute value of the ADC output exceeds the level set by the attack threshold bits in ALC Control Register 2, attack mode is initiated. The PGA gain for both channels is reduced by one step (0.5 dB). The ALC then waits for a time determined by the attack timer bits before sampling the ADC output value again. If the ADC output is still above the threshold, the PGA gain is reduced by a further step. This procedure continues until the ADC output is below the limit set by the attack threshold bits. The initial gains of the PGAs are defined by the ADC left PGA gain register and the ADC right PGA gain register and they can have different values. The ALC subtracts a common gain offset to these values. The ALC preserves any gain difference in dB as defined by these registers. At no time do the PGA gains exceed their initial values. The initial gain setting, therefore, also serves as a maximum value. The limit detection mode bit in ALC Control Register 1 determines how the ALC responds to an ADC output that exceeds the set limits. If this bit is a 1, then both channels must exceed the threshold before the gain is reduced. This mode can be used to prevent unnecessary gain reduction due to spurious noise on a single channel. If the limit detection mode bit is a 0, the gain is reduced when either channel exceeds the threshold.
Limited Recovery Mode
Limited recovery mode offers a compromise between no recovery and normal recovery modes. If the output level of the ADC exceeds the attack threshold, then attack mode is initiated. When attack mode has reduced the PGA gain to suitable levels, the ALC attempts to recover the gain to its original level. If the ADC output level exceeds the level set by the recovery threshold bits, a counter is incremented (GAINCNTR). This counter is incremented at intervals equal to the recovery time selection, if the ADC has any excursion above the recovery threshold. If the counter reaches its maximum value, determined by the GAINCNTR bits in ALC Control Register 1, the PGA gain is deemed suitable and no further gain recovery is attempted. Whenever the ADC output level exceeds the attack threshold, attack mode is reinitiated and the counter is reset.
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ADAV803
Selecting a Sample Rate
The output sample rate of the ADC is always ADC MCLK/256, as shown in Figure 23. By default, the ADC modulator runs at ADC MCLK/2. When the ADC MCLK exceeds 12.288 MHz, the ADC modulator should be set to run at ADC MCLK/4. This is achieved by setting the AMC (ADC Modulator Clock) bit in the ADC Control Register 1. To compensate for the reduced modulator clock speed, a different set of filters is used in the decimator section ensuring that the sample rate remains the same. The AMC bit can also be used to boost the THD + N performance of the ADC at the expense of dynamic range. The improvement is typically 0.5 dB to 1.0 dB and works, because selecting the lower modulator rate reduces the amount of digital noise, improving THD + N, but reduces the oversampling ratio, therefore reducing the dynamic range by a corresponding amount. For best performance of the ADC, avoid using similar frequency clocks from separate sources in the ADAV803. For example, running the ADC from a 12.288 MHz clock connected to MCLKI and using the PLL to generate a separate 12.288 MHz clock for the DAC can reduce the performance of the ADC. This is due to the interaction of the clocks, which generate beat frequencies that can affect the charge on the switch capacitors of the analog inputs.
ATTACK MODE WAIT FOR SAMPLE NO IS A RECOVERY MODE ENABLED? NO IS SAMPLE GREATER THAN ATTACK THRESHOLD? YES DECREASE GAIN BY 0.5dB AND WAIT ATTACK TIME
YES
LIMITED RECOVERY
NORMAL RECOVERY
WAIT FOR SAMPLE
WAIT FOR SAMPLE
IS SAMPLE ABOVE ATTACK THRESHOLD? NO
IS SAMPLE ABOVE ATTACK THRESHOLD? NO
HAS RECOVERY TIME BEEN REACHED? YES
NO
HAS RECOVERY TIME BEEN REACHED? YES
NO
ARE ALL SAMPLES BELOW RECOVERY THRESHOLD? YES
NO
ARE ALL SAMPLES BELOW RECOVERY THRESHOLD? YES
NO
INCREASE GAIN BY 0.5dB INCREMENT GAINCNTR HAS GAIN BEEN FULLY RESTORED? HAS GAIN BEEN FULLY RESTORED? INCREASE GAIN BY 0.5dB WAIT RECOVERY TIME
NO
YES YES
IS GAINCNTR AT MAXIMUM? NO
NO
YES
04756-0-026
Figure 26. ALC Flow Diagram
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ADAV803
DAC SECTION
The ADAV803 has two DAC channels arranged as a stereo pair with single-ended analog outputs. Each channel has its own independently programmable attenuator, adjustable in 128 steps of 0.375 dB per step. The DAC can receive data from the playback or auxiliary input ports, the SRC, the ADC, or the DIR. Each analog output pin sits at a dc level of VREF, and swings 1.0 V rms for a 0 dB digital input signal. A single op amp thirdorder external low-pass filter is recommended to remove high frequency noise present on the output pins. Note that the use of op amps with low slew rate or low bandwidth can cause high frequency noise and tones to fold down into the audio band. Care should be taken in selecting these components. The FILTD and FILTR pins should be bypassed by external capacitors to AGND. The FILTD pin is used to reduce the noise of the internal DAC bias circuitry, thereby reducing the DAC output noise. The voltage at the VREF pin, FILTR, can be used to bias external op amps used to filter the output signals. For applications in which the FILTR is required to drive external op amps, which might draw more than 50 A or have dynamic load changes, extra buffering should be used to preserve the quality of the ADAV803 reference. The digital input data source for the DAC can be selected from a number of available sources by programming the appropriate bits in the datapath control register. Figure 27 shows how the digital data source and the MCLK source for the DAC are selected. Each DAC has an independent volume register giving 256 steps of control, with each step giving approximately 0.375 dB of attenuation. Note that the DACs are muted by default to prevent unwanted pops, clicks, and other noises from appearing on the outputs while the ADAV803 is being configured. Each DAC also has a peak-level register that records the peak value of the digital audio data. Reading the register clears the peak.
TO CONTROL REGISTERS DAC ANALOG OUTPUT DAC TO ZERO FLAG PINS ZERO DETECT MULTI-BIT - MODULATOR INTERPOLATOR VOLUME/MUTE CONTROL FROM DAC DATA PATH MULTIPLEXER
04756-0-028
Selecting a Sample Rate
Correct operation of the DAC is dependent upon the data rate provided to the DAC, the master clock applied to the DAC, and the selected interpolation rate. By default, the DAC assumes that the MCLK rate is 256 times the sample rate, which requires an 8-times oversampling rate. This combination is suitable for sample rates of up to 48 kHz. For a 96 kHz data rate that has a 24.576 MHz MCLK (256 x fS) associated with it, the DAC MCLK divider should be set to divide the MCLK by 2. This prevents the DAC engine from running too fast. To compensate for the reduced MCLK rate, the interpolator should be selected to operate in 4 x (DAC MCLK = 128 x fS). Similar combinations can be selected for different sample rates.
DIR PLL(256 x fS) DIR PLL(512 x fS) PLL2 INTERNAL PLL1 INTERNAL
MCLKI
MCLK DIVIDER
REG 0x65 BITS 3-2
DAC MCLK DAC DAC INPUT
XIN
REG 0x76 BITS 7-5
AUXILIARY IN PLAYBACK DIR ADC REG 0x63 BITS 5-3
04756-0-027
Figure 27. Clock and Datapath Control on the DAC
PEAK DETECTOR
Figure 28. DAC Block Diagram
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ADAV803
SAMPLE RATE CONVERTER (SRC) FUNCTIONAL OVERVIEW
During asynchronous sample rate conversion, data can be converted at the same sample rate or at different sample rates. The simplest approach to an asynchronous sample rate conversion is to use a zero-order hold between the two samplers, as shown in Figure 29. In an asynchronous system, T2 is never equal to T1, nor is the ratio between T2 and T1 rational. As a result, samples at fS_OUT are repeated or dropped, producing an error in the resampling process. The frequency domain shows the wide side lobes that result from this error when the sampling of fS_OUT is convolved with the attenuated images from the SIN(x)/x nature of the zeroorder hold. The images at fS_IN (dc signal images) of the zeroorder hold are infinitely attenuated. Because the ratio of T2 to T1 is an irrational number, the error resulting from the resampling at fS_OUT can never be eliminated. The error can be significantly reduced, however, through interpolation of the input data at fS_IN. Therefore, the sample rate converter in the ADAV803 is conceptually interpolated by a factor of 220.
IN ZERO-ORDER HOLD OUT
IN INTERPOLATE BY N LOW-PASS FILTER ZERO-ORDER HOLD OUT
fS_IN
fS_OUT
TIME DOMAIN OF fS_IN SAMPLES
TIME DOMAIN OUTPUT OF THE LOW-PASS FILTER
TIME DOMAIN OF fS_OUT RESAMPLING
TIME DOMAIN OF THE ZERO-ORDER HOLD OUTPUT
Figure 30. SRC Time Domain
fS_IN =1/T1
ORIGINAL SIGNAL
fS_OUT = 1/T2
SAMPLED AT fS_IN SIN(X)/X OF ZERO-ORDER HOLD SPECTRUM OF ZERO-ORDER HOLD OUTPUT
In the frequency domain shown in Figure 31, the interpolation expands the frequency axis of the zero-order hold. The images from the interpolation can be sufficiently attenuated by a good low-pass filter. The images from the zero-order hold are now pushed by a factor of 220 closer to the infinite attenuation point of the zero-order hold, which is fS_IN x 220. The images at the zero-order hold are the determining factor for the fidelity of the output at fS_OUT.
IN INTERPOLATE BY N LOW-PASS FILTER ZERO-ORDER HOLD OUT
fS_IN
SPECTRUM OF fS_OUT SAMPLING
fS_OUT
FREQUENCY RESPONSE OF fS_OUT CONVOLVED WITH ZERO-ORDER HOLD SPECTRUM
Figure 29. Zero-Order Hold Used by fS_ OUT to Resample Data from fS_IN
04756-0-029
fS_OUT
2 x fS_OUT
FREQUENCY DOMAIN OF SAMPLES AT fS_IN
fS_IN
FREQUENCY DOMAIN OF THE INTERPOLATION
220 x fS_IN
Conceptual High Interpolation Model
Interpolation of the input data by a factor of 220 involves placing (220 - 1) samples between each fS_IN sample. Figure 30 shows both the time domain and the frequency domain of interpolation by a factor of 220. Conceptually, interpolation by 220 involves the steps of zero-stuffing (220 - 1) number of samples between each fS_IN sample and convolving this interpolated signal with a digital low-pass filter to suppress the images. In the time domain, it can be seen that fS_OUT selects the closest fS_IN x 220 sample from the zero-order hold, as opposed to the nearest fS_IN sample in the case of no interpolation. This significantly reduces the resampling error.
SIN(X)/X OF ZERO-ORDER HOLD FREQUENCY DOMAIN OF fS_OUT RESAMPLING 220 x fS_IN
FREQUENCY DOMAIN AFTER RESAMPLING
220 x fS_IN
Figure 31. Frequency Domain of the Interpolation and Resampling
Rev. 0 | Page 19 of 56
04756-0-031
04756-0-030
ADAV803
The worst-case images can be computed from the zero-order hold frequency response: maximum image = sin (x F/fS_INTERP)/(x F/fS_INTERP) where: F is the frequency of the worst-case image that would be 220 x fS_IN fS_IN/2. fS_INTERP is fS_IN x 220. The following worst-case images would appear for fS_IN equal to 192 kHz: Image at fS_INTERP - 96 kHz = -125.1 dB Image at fS_INTERP + 96 kHz = -125.1 dB must be lowered, because the Nyquist frequency of the output samples is less than the Nyquist frequency of the input samples. To move the cutoff frequency of the antialiasing filter, the coefficients are dynamically altered and the length of the convolution is increased by a factor of (fS_IN/fS_OUT). This technique is supported by the Fourier transform property that, if f(t) is F(), then f(k x t) is F(/k). Thus, the range of decimation is limited by the size of the RAM.
SRC Architecture
The architecture of the sample rate converter is shown in Figure 32. The sample rate converter's FIFO block adjusts the left and right input samples and stores them for the FIR filter's convolution cycle. The fS_IN counter provides the write address to the FIFO block and the ramp input to the digital servo loop. The ROM stores the coefficients for the FIR filter convolution and performs a high order interpolation between the stored coefficients. The sample rate ratio block measures the sample rate for dynamically altering the ROM coefficients and scaling of the FIR filter length as well as the input data. The digital servo loop automatically tracks the fS_IN and fS_OUT sample rates and provides the RAM and ROM start addresses for the start of the FIR filter convolution.
RIGHT DATA IN LEFT DATA IN ROM A FIFO ROM B ROM C ROM D HIGH ORDER INTERP
Hardware Model
The output rate of the low-pass filter in Figure 30 is the interpolation rate: 220 x 192,000 kHz = 201.3 GHz Sampling at a rate of 201.3 GHz is clearly impractical, not to mention the number of taps required to calculate each interpolated sample. However, because interpolation by 220 involves zero-stuffing 220-1 samples between each fS_IN sample, most of the multiplies in the low-pass FIR filter are by zero. A further reduction can be realized, because only one interpolated sample is taken at the output at the fS_OUT rate, so only one convolution needs to be performed per fS_OUT period instead of 220 convolutions. A 64-tap FIR filter for each fS_OUT sample is sufficient to suppress the images caused by the interpolation. One difficulty with the above approach is that the correct interpolated sample must be selected upon the arrival of fS_OUT. Because there are 220 possible convolutions per fS_OUT period, the arrival of the fS_OUT clock must be measured with an accuracy of 1/201.3 GHz = 4.96 ps. Measuring the fS_OUT period with a clock of 201.3 GHz frequency is clearly impossible; instead, several coarse measurements of the fS_OUT clock period are made and averaged over time. Another difficulty with the above approach is the number of coefficients required. Because there are 220 possible convolutions with a 64-tap FIR filter, there must be 220 polyphase coefficients for each tap, which requires a total of 226 coefficients. To reduce the number of coefficients in ROM, the SRC stores a small subset of coefficients and performs a high order interpolation between the stored coefficients. The above approach works when fS_OUT > fS_IN. However, when the output sample rate, fS_OUT, is less than the input sample rate, fS_IN, the ROM starting address, input data, and length of the convolution must be scaled. As the input sample rate rises over the output sample rate, the antialiasing filter's cutoff frequency
fS_IN
COUNTER
DIGITAL SERVO LOOP FIR FILTER SAMPLE RATE RATIO L/R DATA OUT
04756-0-032
fS_IN fS_OUT
SAMPLE RATE RATIO EXTERNAL RATIO
Figure 32. Architecture of the Sample Rate Converter
The FIFO receives the left and right input data and adjusts the amplitude of the data for both the soft muting of the sample rate converter and the scaling of the input data by the sample rate ratio before storing the samples in the RAM. The input data is scaled by the sample rate ratio, because, as the FIR filter length of the convolution increases, so does the amplitude of the convolution output. To keep the output of the FIR filter from saturating, the input data is scaled down by multiplying it by (fS_OUT/fS_IN) when fS_OUT < fS_IN. The FIFO also scales the input data for muting and unmuting of the SRC. The RAM in the FIFO is 512 words deep for both left and right channels. An offset to the write address provided by the fS_IN counter is added to prevent the RAM read pointer from overlapping the write address. The minimum offset on the SRC is 16 samples. However, the group delay and mute-in register can be used to increase this offset.
Rev. 0 | Page 20 of 56
ADAV803
The number of input samples added to the write pointer of the FIFO on the SRC is 16 plus Bit 6 to Bit 0 of the group delay register. This feature is useful in varispeed applications to prevent the read pointer to the FIFO from running ahead of the write pointer. When set, Bit 7 of the group delay and mute-in register soft-mutes the sample rate. Increasing the offset of the write address pointer is useful for applications in which small changes in the sample rate ratio between fS_IN and fS_OUT are expected. The maximum decimation rate can be calculated from the RAM word depth and the group delay as (512 - 16)/64 taps = 7.75 for short group delay and (512 - 64)/64 taps = 7 for long group delay. The digital servo loop is essentially a ramp filter that provides the initial pointer to the address in RAM and ROM for the start of the FIR convolution. The RAM pointer is the integer output of the ramp filter, and the ROM is the fractional part. The digital servo loop must provide excellent rejection of jitter on the fS_IN and fS_OUT clocks, as well as measure the arrival of the fS_OUT clock within 4.97 ps. The digital servo loop also divides the fractional part of the ramp output by the ratio of fS_IN/fS_OUT to dynamically alter the ROM coefficients when fS_IN > fS_OUT.
PLLINT1 PLLINT2 MCLKI XIN
servo loop is settling down to a reasonable value, the digital servo loop returns to normal (or slow) mode. During fast mode, the MUTE_OUT bit in the sample rate error register is asserted to let the user know that clicks or pops might be present in the digital audio data. The output of the SRC can be muted by asserting Bit 7 of the group delay and mute register until the SRC has changed to slow mode. The MUTE_OUT bit can be set to generate an interrupt when the SRC changes to slow mode, indicating that the data is being sample rate converted accurately. The frequency responses of the digital servo loop for fast mode and slow mode are shown in Figure 34. The FIR filter is a 64-tap filter when fS_OUT fS_IN and is (fS_IN/fS_OUT) x 64 taps when fS_IN > fS_OUT. The FIR filter performs its convolution by loading in the starting address of the RAM address pointer and the ROM address pointer from the digital servo loop at the start of the fS_OUT period. The FIR filter then steps through the RAM by decrementing its address by 1 for each tap, and the ROM pointer increments its address by the (fS_OUT/fS_IN) x 220 ratio for fS_IN > fS_OUT or 220 for fS_OUT fS_IN. Once the ROM address rolls over, the convolution is completed.
0 -20 -40 -60 SLOW MODE FAST MODE
MAGNITUDE (dB)
-80 -100 -120 -140 -160 -180 -200
04756-0-034
DIR PLL(512 x fS)
DIR PLL(256 x fS)
REG 0x76 BIT 1
REG 0x76 BIT 0
ICLK2
ICLK1
-220 0.01
0.1
1
10 100 FREQUENCY (Hz)
1k
10k
100k
REG 0x00 BITS 1-0
Figure 34. Frequency Response of the Digital Servo Loop. fS_IN is the X-Axis, fS_OUT = 192 KHz, Master Clock is 30 MHz
SRC MCLK SRC SRC OUTPUT REG 0x62 BITS 7-6 SRC INPUT
AUXILIARY IN PLAYBACK DIR
04756-0-033
ADC
Figure 33. Clock and Datapath Control on the SCR
The digital servo loop is implemented with a multirate filter. To settle the digital servo loop filter more quickly upon startup or a change in the sample rate, a fast mode has been added to the filter. When the digital servo loop starts up or the sample rate is changed, the digital servo loop enters fast mode to adjust and settle on the new sample rate. Upon sensing that the digital
The convolution is performed for both the left and right channels, and the multiply accumulate circuit used for the convolution is shared between the channels. The fS_IN/fS_OUT sample rate ratio circuit is used to dynamically alter the coefficients in the ROM when fS_IN > fS_OUT. The ratio is calculated by comparing the output of an fS_OUT counter to the output of an fS_IN counter. If fS_OUT > fS_IN, the ratio is held at one. If fS_IN > fS_OUT, the sample rate ratio is updated, if it is different by more than two fS_OUT periods from the previous fS_OUT to fS_IN comparison. This is done to provide some hysteresis to prevent the filter length from oscillating and causing distortion.
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ADAV803
PLL SECTION
The ADAV803 features a dual PLL configuration to generate independent system clocks for asynchronous operation. Figure 37 shows the block diagram of the PLL section. The PLL generates the internal and system clocks from a 27 MHz clock. This clock is generated either by a crystal connected between XIN and XOUT, as shown in Figure 35, or from an external clock source connected directly to XIN. A 54 MHz clock can also be used, if the internal clock divider is used.
C XTAL C
Table 7. PLL Frequency Selection Options
PLL 1 2A 2B Sample Rate (fS) 32/44.1/48 kHz 64/88.2/96 kHz 32/44.1/48 kHz 64/88.2/96 kHz Same as fS selected For PLL 2A MCLK Selection Normal fS Double fS 256/384 x fS 512/768 x fS 256/384 x fS 256/384 x fS 512/768 x fS 256/384 x fS 512 x fS 512 x fS
Figure 35. Crystal Connection
Both PLLs (PLL1 and PLL2) can be programmed independently and can accommodate a range of sampling rates (32/44.1/48 kHz) with selectable system clock oversampling rates of 256 and 384. Higher oversampling rates can also be selected by enabling the doubling of the sampling rate to give 512 or 768 x fS ratios. Note that this option also allows oversampling ratios of 256 or 384 at double sample rates of 64/88.2/96 kHz. The PLL outputs can be routed internally to act as clock sources for the other component blocks such as the ADC, DAC, and so on. The outputs of the PLLs are also available on the three SYSCLK pins. Figure 38 shows how the PLLs can be configured to provide the sampling clocks.
The PLLs require some external components to operate correctly. These components, shown in Figure 36, form a loop filter that integrates the current pulses from a charge pump and produces a voltage that is used to tune the VCO. Good quality capacitors, such as PPS film, are recommended. Figure 37 shows a block diagram of the PLL section, including master clock selection. Figure 38 shows how the clock frequencies at the clock output pins, SYSCLK1 to SYSCLK 3, and the internal PLL clock values, PLL1 and PLL2, are selected. The clock nodes, PLL1 and PLL2, can be used as master clocks for the other blocks in the ADAV803 such as the DAC or ADC. The PLL has separate supply and ground pins, which should be as clean as possible to prevent electrical noise from being converted into clock jitter by coupling onto the loop filter pins.
AVDD
XIN
XOUT
04756-0-035
100nF PLL BLOCK 6.8nF
04756-0-036
04756-0-037
3.3 PLL_LFx
Figure 36. PLL Loop Filter
PLL_LF1 REG 0x78 BIT 6 /2 XOUT MCLKO REG 0x74 BIT 5 /2 MCLKI REG 0x78 BIT 7 REG 0x74 BIT 4 PHASE DETECTOR AND LOOP FILTER
XIN
PHASE DETECTOR AND LOOP FILTER
VCO
OUTPUT SCALER N1 PLL1
SYSCLK1
/N
VCO
OUTPUT SCALER N2 PLL2
SYSCLK2
/N
OUTPUT SCALER N3
SYSCLK3
PLL_LF2
Figure 37. PLL Section Block Diagram
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ADAV803
PLL1 MCLK PLL2 MCLK PLL1
48kHz 32kHz 44.1kHz
REG 0x75 BITS 3-2
REG 0x75 BIT 0 x2 FS1 REG 0x77 BIT 0 /2
SYSCLK1
256 384
REG 0x75 BIT 1
PLLINT1
256 384
REG 0x75 BIT 5
REG 0x75 BIT 4 x2 FS2 REG 0x77 BITS 2-1 /2 /2 FS3
PLL1
SYSCLK2
48kHz 32kHz 44.1kHz
REG 0x75 BITS 7-6
SYSCLK3
Figure 38. PLL Clocking Scheme
SPDIF TRANSMITTER AND RECEIVER
The ADAV803 contains an integrated SPDIF transmitter and receiver. The transmitter consists of a single output pin, DITOUT, on which the biphase encoded data appears. The SPDIF transmitter source can be selected from the different blocks making up the ADAV803. Additionally, the clock source for the SPDIF transmitter can be selected from the various clock sources available in the ADAV803. The receiver uses two pins, DIRIN and DIR_LF. DIRIN accepts the SPDIF input data stream. The DIRIN pin can be configured to accept a digital input level, as defined in the Specifications section, or an input signal with a peak-to-peak level of 200 mV minimum, as defined by the IEC60958-3 specification. DIR_LF is a loop filter pin, required by the internal PLL, which is used to recover the clock from the SPDIF data stream. The components shown in Figure 42 form a loop filter, which integrates the current pulses from a charge pump and produces a voltage that is used to tune the VCO of the clock recovery PLL. The recovered audio data and audio clock can be routed to the different blocks of the ADAV803, as required. Figure 39 shows a conceptual diagram of the DIRIN block.
C* SPDIF DIRIN
REG 0x74 BIT 4
04756-0-038
256 512
REG 0x74 BIT 0
PLLINT1
SPDIF RECEIVER
DC LEVEL
COMPARATOR
04756-0-039
* EXTERNAL CAPACITOR IS ONLY REQUIRED FOR VARIABLE LEVEL SPDIF INPUTS.
Figure 39. DIRIN Block
ADC DIR PLAYBACK AUXILIARY IN SRC REG 0x63 BITS 2-0
04756-0-040
DIT INPUT
DIT
DITOUT
Figure 40. Digital Output Transmitter Block Diagram
DIRIN DIR AUDIO DATA
04756-0-041
RECOVERED CLOCK
Figure 41. Digital Input Receiver Block Diagram
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ADAV803
AVDD
PREAMBLES
100F DIR BLOCK 6.8nF
04756-0-042
X LEFT CH Y RIGHT CH Z LEFT CH Y RIGHT CH X LEFT CH Y RIGHT CH
04756-0-044
3 DIR_LF
SUBFRAME FRAME 191
SUBFRAME FRAME 1 FRAME 0
Figure 42. DIR Loop Filter Components
Figure 44. Preambles, Frames, and Subframes
Serial Digital Audio Transmission Standards
The ADAV803 can receive and transmit SPDIF, AES/EBU, and IEC-958 serial streams. SPDIF is a consumer audio standard, and AES/EBU is a professional audio standard. IEC-958 has both consumer and professional definitions. This data sheet is not intended to fully define or to provide a tutorial for these standards. Contact the international standards-setting bodies for the full specifications. All these digital audio communication schemes encode audio data and audio control information using the biphase-mark method. This encoding method minimizes the dc content of the transmitted signal. As can be seen from Figure 43, 1s in the original data end up with midcell transitions in the biphasemark encoded data, while 0s in the original data do not. Note that the biphase-mark encoded data always has a transition between bit boundaries.
CLOCK (2 TIMES BIT RATE) 0 DATA 1 1 1 0 0
The biphase-mark encoding violations are shown in Figure 45. Note that all three preambles include encoding violations. Ordinarily, the biphase-mark encoding method results in a polarity transition between bit boundaries.
1 1 1 0 0 0 1 0
PREAMBLE X
1
1
1
0
0
1
0
0
PREAMBLE Y
1
1
1
0
1
0
0
0
Figure 45. Preambles
Figure 43. Biphase-Mark Encoding
Digital audio-communication schemes use preambles to distinguish among channels (called subframes) and among longer-term control information blocks (called frames). Preambles are particular biphase-mark patterns, which contain encoding violations that allow the receiver to uniquely recognize them. These patterns and their relationship to frames and subframes are shown in Table 8 and Figure 44. Table 8. Biphase-Mark Encode Preamble
X Y Z Biphase Patterns 11100010 or 00011101 11100100 or 00011011 11101000 or 00010111 Channel Left Right Left and CS block start
04756-0-043
BIPHASE-MARK DATA
The serial digital audio communication scheme is organized using a frame and subframe construction. There are two subframes per frame (ordinarily the left and right channel). Each subframe includes the appropriate 4-bit preamble, up to 24 bits of audio data, a validity (V) bit, a user (U) bit, a channel status (C) bit, and an even parity (P) bit. The channel status bits and the user bits accumulate over many frames to convey control information. The channel status bits accumulate over a 192 frame period (called a channel status block). The user bits accumulate over 1,176 frames when the interconnect is implementing the so-called subcode scheme (EIAJ CP-2401). The organization of the channel status block, frames, and subframes is shown in Table 9 and Table 10. Note that the ADAV803 supports the professional audio standard from a software point of view only. The digital interface supports only consumer mode. Table 9. Consumer Audio Standard
Data Bits Address N N+1 N+2 N+3 7 6 Channel Status 5 4 Emphasis 3 2 Copyright 1 NonAudio 0 Pro/ Con =0
N+4 N + 5 to Reserved (N + 23) N = 0x20 for receiver channel status buffer. N = 0x38 for transmitter channel status buffer.
Category Code Channel Number Source Number Clock Reserved Sampling Frequency Accuracy Reserved Word Length
Rev. 0 | Page 24 of 56
04756-0-045
PREAMBLE Z
ADAV803
Table 10. Professional Audio Standard
Address N N+1 7 6 Sample Frequency 5 Lock Data Bits 4 3 Emphasis 2 1 NonAudio 0 Pro/ Con =1
The standards allow the channel status bits in each subframe to be independent, but ordinarily the channel status bit in the two subframes of each frame are the same. The channel status bits are defined differently for the consumer audio standards and the professional audio standards. The 192 channel status bits are organized into 24 bytes and have the interpretations shown in Table 9 and Table 10. The SPDIF transmitter and receiver have a comprehensive register set. The registers give the user full access to the functions of the SPDIF block, such as detecting nonaudio and validity bits, Q subcodes, preambles, and so on. The channel status bits as defined by the IEC60958 and AES3 specifications are stored in register buffers for ease of use. An autobuffering function allows channel status bits and user bits read by the receiver to be copied directly to the transmitter block, removing the need for user intervention.
Figure 47. Receiver User Bit Buffer
The SPDIF receive buffer is updated continuously by the incoming SPDIF stream. Once all the channel status bits for the block (192 for Channel A and 192 for Channel B) are received, the bits are copied into the receiver channel status buffer. This buffer stores all 384 bits of channel status information, and the RxCSSWITCH bit in the channel status switch buffer register determines whether the Channel A or the Channel B status bits are required to be read. The receive channel status bit buffer is 24 bytes long and spans the address range from 0x20 to 0x37. Because the channel status bits of an SPDIF stream rarely change, a software interrupt/flag bit, RxCSBINT, is provided to notify the host control that either a new block of channel status bits is available or that the first five bytes of channel status information have changed from a previous block. The function of the RxCSBINT is controlled by the RxBCONF3 bit in the receiver buffer configuration register. The size of the user bit buffer can be set by programming the RxBCONF0 bit in the receiver buffer configuration register, as shown in Table 11.
Receiver Section
The ADAV803 uses a double-buffering scheme to handle reading channel status and user bit information. The channel status bits are available as a memory buffer, taking up 24 consecutive register locations. The user bits are read using an indirect memory addressing scheme, where the receiver user- bit indirect-address register is programmed with an offset to the
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User Bit Management Channel Mode Alignment Use of Auxiliary Mode N+2 Source Word Length Level Sample Bits N+3 Channel Identification fS Digital Audio N+4 Reserved ScalSample Frequency (fS) Reference ing Signal N+5 Reserved N+6 Alphanumeric Channel Origin Data--First Character N+7 Alphanumeric Channel Origin Data N+8 Alphanumeric Channel Origin Data N+9 Alphanumeric Channel Origin Data--Last Character N + 10 Alphanumeric Channel Destination Data--First Character N + 11 Alphanumeric Channel Destination Data N + 12 Alphanumeric Channel Destination Data N + 13 Alphanumeric Channel Destination Data--Last Character N + 14 Local Sample Address Code--LSW N + 15 Local Sample Address Code N + 16 Local Sample Address Code N + 17 Local Sample Address Code--MSW N + 18 Time of Day Code--LSW N + 19 Time of Day Code N + 20 Time of Day Code N + 21 Time of Day Code--MSW N + 22 Reliability Flags Reserved N + 23 Cyclic Redundancy Check Character (CRCC) N = 0x20 for receiver channel status buffer. N = 0x38 for transmitter channel status buffer.
user bit buffer, and the receiver user bit data register can be read to determine the user bits at that location. Reading the receiver user bit data register automatically updates the indirect address register to the next location in the buffer. Typically, the receiver user bit indirect-address register is programmed to zero (the start of the buffer), and the receiver user bit data register is read repeatedly until all the buffer's data has been read. Figure 46 and Figure 47 show how receiving the channel status bits and user bits is implemented.
DIRIN CHANNEL STATUS A (24 x 8 BITS) CHANNEL STATUS B (24 x 8 BITS) SECONDBUFFER RECEIVE CS BUFFER (0x20-0x37) RxCSSWITCH
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SPDIF RECEIVE BUFFER FIRST BUFFER
Figure 46. Channel Status Buffer
SPDIFIN
0.....7 8.....15 16.....23
0.....7 8.....15 16.....23 ADDRESS = 0x50 RECEIVER USER BIT INDIRECT ADDRESS REGISTER
FIRST BUFFER
USER-BIT BUFFER
ADDRESS = 0x51 RECEIVER USER BIT DATA REGISTER
ADAV803
Table 11. RxBCONF3 Functionality
RxBCONF0 0 1 Receiver User Bit Buffer Size 384 bits with Preamble Z as the start of the block. 768 bits with Preamble Z as the start of the block.
Transmitter Operation
The SPDIF transmitter has a similar buffer structure to the receive section. The transmitter channel status buffer occupies 24 bytes of the register map. This buffer is long enough to store the 192 bits required for one channel of channel status information. Setting the TxCSSWITCH bit determines if the data loaded to the transmitter channel status buffer is intended for Channel A or Channel B. In most cases, the channel status bits for Channel A and Channel B are the same, in which case setting the Tx_A/B_Same bit reads the data from the transmitter channel status buffer and transmits it on both channels. Because the channel status information is rarely changed during transmission, the information contained in the buffer is transmitted repeatedly. The Disable_Tx_Copy bit can be used to prevent the channel status bits from being copied from the transmitter CS buffer into the SPDIF transmitter buffer until the user has finished loading the buffers. This feature is typically used, if the Channel A data and Channel B data are different. Setting the bit prevents the data from being copied. Clearing the bit allows the data to be copied and then transmitted. Figure 48 shows how the buffers are organized.
DITOUT
The updating of the user bit buffer is controlled by Bits RxBCONF2-1 and Bit 7 to Bit 4 of the channel status register, as shown in Table 12 and Table 13. Table 12. RxBCONF2-1 Functionality
RxBCONF Bit 2 Bit 1 0 0 0 1 1 0 Receiver User Bit Buffer Configuration User bits are ignored. Update second buffer when first buffer is full. Format according to Byte 1, Bit 4 to Bit 7, if PRO bit is set. Format according to IEC60958-3, if PRO bit is clear.
Table 13. Automatic User Bit Configuration
Bits 76 00 01 1 0 5 0 0 0 4 0 0 0 Automatic Receiver User Bit Buffer Configuration User bits are ignored. AES-18 format: the user bit buffer is treated in the same way as when RxBCONF2-1 = 0b01. User bit buffer is updated in the same way as when RxBCONF2-1 = 0b01 and RxBCONF0 = 0b00. User-defined format: the user bit buffer is treated in the same way as when RxBCONF2-1 = 0b01.
1
1
0
0
When the user bit buffer has been filled, the RxUBINT interrupt bit in the interrupt status register is set, provided that the RxUBINT mask bit is set, to indicate that the buffer has new information and can be read. For the special case when the user data is formatted according to the IEC60958-3 standard into messages made of information units, called IUs, the zeros stuffed between each IU and each message are removed and only the IUs are stored. Once the end of the message is sensed by more that eight zeros between IUs, the user bit buffer is updated with the complete message and the first buffer begins looking for the start of the next message. Each IU is stored as a byte consisting of 1, Q, R, S, T, U, V, and W bits (see the IEC60958-3 specification for more information). When 96 IUs are received, the Q subcode of the IUs is stored in the Q subcode buffer, consisting of 10 bytes. The Q subcode is the Q bits taken from each of the 96 IUs. The first 10 bytes (80 bits) of the Q subcode contain information sent by CD, MD, and DAT systems. The last 16 bits of the Q subcode are used to perform a CRC check of the Q subcode. If an error occurs in the CRC check of the Q subcode, the QCRCERROR bit is set. This is a sticky bit that remains high until the register is read.
TxCSSWITCH
Figure 48. Transmitter Channel Status Buffer
As with the receiver section, the transmitted user bits are also double-buffered. This is required, because, unlike the channel status bits, the user bits do not necessarily repeat themselves. The user bits can be buffered in various configurations, as listed in Table 14. Transmission of the user bits is determined by the state of the BCONF3 bit. If the bit is 0, the user bits begin transmitting right away without alignment to the Z preamble. If this bit is 1, the user bits do not start transmitting until a Z preamble occurs when the TxBCONF2-1 bits are 01. Table 14. Transmitter User Bit Buffer Configurations
TxBCONF2-1 Bit 2 Bit 1 0 0 0 1 1 0 Transmitter User Bit Buffer Configuration Zeros are transmitted for the user bits. Host writes user bits to the buffer until it is full. Writes the user bits to the buffer in IUs specified by IEC60958-3 and transmits them according to the standard. First 10 bytes of the user-bit buffer are configured to store a Q subcode.
1
1
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TRANSMIT CS BUFFER (0x38-0x4F)
CHANNEL STATUS A (24 x 8 BITS) CHANNEL STATUS B (24 x 8 BITS)
SPDIF TRANSMIT BUFFER
ADAV803
Table 15. Transmitter User Bit Buffer Size
TxBCONF0 0 1 Buffer Size 384 bits with Preamble Z as the start of the block. 768 bits with Preamble Z as the start of the block.
bytes contain information, these bytes might be repeated or dropped, in which case information can be lost. It is up to the user to determine how to handle this case. When the user bits are transmitted according to the IEC60958-3 format, the messages contained in the user bits can still be sent without dropping or repeating messages. Because zero-stuffing is allowed between IUs and messages, zeros can be added or subtracted to preserve the messages. When the transmitter sample rate is greater than the receiver sample rate, extra zeros are stuffed between the messages. When the sample rate of the transmitter is less than the sample rate of the receiver, the zeros stuffed between the messages are subtracted. If there are not enough zeros between the messages to be subtracted, the zeros between IUs are subtracted as well. The Zero_Stuff_IU bit in the autobuffer register enables the adding or subtracting of zeros between messages.
By using sticky bits and interrupts, the transmit buffers can notify the host or microcontroller when the first user bit buffer has been updated and when the second transmit user bit buffer is full. The sticky bit, TxUBINT, is set when the transmit user bit buffer has been updated and the second transmit user bit buffer is ready to accept new user bits. The sticky bit, TxFBINT, is set whenever the second transmit user bit buffer is full. Any new writes to this buffer are ignored until the first transmit buffer is updated. These two bits are located in the interrupt status register. When the host reads the interrupt status register, these bits are cleared. Interrupts for the TxUBINT and TxFBINT sticky bits can be enabled by setting the TxUBMASK and TxFBMASK bits, respectively, in the interrupt status mask register.
SPDIF 0
Interrupts
The ADAV803 provides interrupt bits to indicate the presence of certain conditions that require attention. Reading the interrupt status register allows the user to determine if any of the interrupts have been asserted. The bits of the interrupt status register remain high, if set, until the register is read. Two bits, SRCError and RxError, indicate interrupt conditions in the sample rate converter and an SPDIF receiver error, respectively. Both these conditions require a read of the appropriate error register to determine the exact cause of the interrupt. Each interrupt in the interrupt status register has an associated mask bit in the interrupt status mask register. The interrupt mask bit must be set for the corresponding interrupt to be generated. This feature allows the user to determine which functions should be responded to. The dual function pin ZEROL/INT can be set to indicate the presence of no audio data on the left channel or the presence of an interrupt set in the interrupt status register. As shown in Table 16, the function of this pin is selected by the INTRPT bit in DAC Control Register 4. Table 16. ZEROL/INT Pin Functionality
INTRPT 0 1 Pin Functionality Pin functions as a ZEROL flag pin. Pin functions as an interrupt pin.
0.....7 8.....15 ADDRESS = 0x52 TRANSMITTER USER BIT INDIRECT ADDRESS REGISTER USER-BIT BUFFER 16.....23
0.....7 8.....15 16.....23
ADDRESS = 0x53 TRANSMITTER USER BIT DATA REGISTER
SECOND BUFFER
Figure 49. Transmitter User Bit Buffer
Autobuffering
The ADAV803 SPDIF receiver and transmitter sections have an autobuffering mode allowing the channel status and user bits to be copied automatically from the receiver to the transmitter without user intervention. The channel status and user bits can be independently selected for autobuffering using the Auto_CSBits and Auto_UBits bits, respectively, in the autobuffer register. When the receiver and transmitter are running at the same sample rate, the transmitted channel status and user bits are the same as the received channel-status and user bits. In many systems, however, it is likely that the receiver and transmitter are not running at the same frequency. When the transmitter sample rate is higher than the receiver sample rate, the channel status and user bit block is sometimes repeated. When the transmitter sample rate is lower than the receiver sample rate, the channel status and user bit blocks might be dropped. Because the first five bytes of the channel status are typically constant, they can be repeated or dropped with no information loss. However, if the PRO bit in the channel status is set and the local sample address code and time-of-day code
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SERIAL DATA PORTS
The ADAV803 contains four flexible serial ports (SPORTs) to allow data transfer to and from the codec. All four SPORTs are independent and can be configured as master or slave ports. In slave mode, the xLRCLK and xBCLK signals are inputs to the serial ports. In master mode, the serial port generates the xLRCLK and xBCLK signals. The master clock for the SPORT can be selected from a number of sources, as shown in Figure 50.
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ADAV803
REG 0x76 BITS 4-2 DIR PLL(512 x fS) DIR PLL(256 x fS) PLLINT1 PLLINT2 MCLKI XIN REG 0x76 BITS 7-5 DIR PLL(512 x fS) DIR PLL(256 x fS) PLLINT1 PLLINT2 MCLKI XIN ADC MCLK OUTPUT PORT OLRCLK OBCLK OSDATA
ICLK1 ICLK2 PLL CLOCK DAC MCLK
REG 0x06 BITS 4-3 INPUT PORT ILRCLK IBCLK ISDATA
Care should be taken to ensure that the clock rate is appropriate for whatever block is connected to the serial port. For example, if the ADC is running from the MCLKI input at 256 x fS, then the master clock for the SPORT should also run from the MCLKI input to ensure that the ADC and serial port are synchronized. The SPORTs can be set to transmit or receive data in I2S, leftjustified or right-justified formats with different word lengths by programming the appropriate bits in the playback register, auxiliary input port register, record register, and auxiliary output port-control register. Figure 51 is a timing diagram of the serial data port formats.
Figure 50. SPORT Clocking Scheme
LRCLK BCLK SDATA MSB
LEFT CHANNEL
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REG 0x04 BITS 4-3 REG 0x77 BITS 4-3 REG 0x00 SRC REG 0x00 BITS 1-0 MCLKI BITS 3-2 MCLK ICLK1 XIN DIVIDER PLLINT1 DIR PLL(512 x fS) PLLINT2 DIVIDER DIR PLL(256 x fS) REG 0x00 MCLKI BITS 1-0 XIN DIVIDER PLLINT1 ICLK2 REG 0x00 PLLINT2 BITS 4-5 REG 0x76 BITS 1-0
ICLK1 ICLK2 PLL CLOCK
Clocking Scheme
The ADAV803 provides a flexible choice of on-chip and offchip clocking sources. The on-chip oscillator with dual PLLs is intended to offer complete system clocking requirements for use with available MPEG encoders, decoders, or a combination of codecs. The oscillator function is designed for generation of a 27 MHz video clock from a 27 MHz crystal connected between the XIN and XOUT pins. Capacitors must also be connected between these pins and DGND, as shown in Figure 35. The capacitor values should be specified by the crystal manufacturer. A square wave version of the crystal clock is output on the MCLKO pin. If the system has a 27 MHz clock available, this clock can be connected directly to the XIN pin.
RIGHT CHANNEL
LSB
MSB
LSB
LEFT-JUSTIFIED MODE -- 16 BITS TO 24 BITS PER CHANNEL
LRCLK BCLK SDATA MSB
LEFT CHANNEL
RIGHT CHANNEL
LSB
MSB
LSB
I2S MODE -- 16 BITS TO 24 BITS PER CHANNEL
LRCLK BCLK
LEFT CHANNEL
RIGHT CHANNEL
RIGHT-JUSTIFIED MODE -- SELECT NUMBER OF BITS PER CHANNEL
Figure 51. Serial Data Modes
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SDATA
MSB
LSB
MSB
LSB
ADAV803
Datapath
The ADAV803 features a digital input/output switching/ multiplexing matrix that gives flexibility to the range of possible input and output connections. Digital input ports include playback and auxiliary input (both 3-wire digital), and S/PDIF (single-wire to the on-chip receiver). Output ports include the record and auxiliary output ports (both 3-wire digital) and the S/PDIF port (single-wire from the on-chip transmitter). Internally, the DIR and DIT are interfaced via 3-wire interfaces. The datapath for each input and output port is selected by programming Datapath Control Registers 1 and 2. Figure 52 shows the internal datapath structure of the ADAV803.
PLL OSCILLATOR RECORD DATA OUTPUT
ADC
AUX DATA OUTPUT
REFERENCE SRC DAC DIT
Figure 52. Datapath
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CONTROL REGISTERS
PLAYBACK DATA INPUT
AUX DATA INPUT
DIR
ADAV803 INTERFACE CONTROL
The ADAV803 has a dedicated control port to allow the internal registers of the ADAV803 to be accessed. Each of the internal registers is eight bits wide. Where bits are described as reserved (RES), these bits should be programmed as zero. Initiating a write operation to the ADAV803 involves sending a start condition and then sending the device address with the R/W set low. The ADAV803 responds by issuing an ACK to indicate that it has been addressed. The user then sends a second frame telling the ADAV803 which register is required to be written to. The 7-bit register address is left-shifted to make the eight bits that the frame requires. Another ACK is issued by the ADAV803. Finally the user can send another frame with the eight data bits required to be written to the register. A third ACK is issued by the ADAV803, after which the user can send a stop condition to complete the data transfer. A read operation requires that the user first write to the ADAV803 to point to the correct register and then read the data. This is achieved by sending a start condition followed by the device address frame, with R/W low, and then the register address frame. Following the ACK from the ADAV803, the user must issue a repeated start condition. This is identical to a start condition. The next frame is the device address with R/W set high. On the next frame, the ADAV803 outputs the register data on the SDA line. A stop condition completes the read operation. Figure 53 and Figure 54 show examples of writing to and reading from the DAC left volume register (Address 0b1101000).
I2C INTERFACE
The I2C interface of the ADAV803 is a 2-wire interface consisting of a clock line, SCL, and a data line, SDA. SDA is bidirectional; the ADAV803 drives SDA to either acknowledge the master, ACK, or send data during a read operation. The SDA pin for the I2C port is an open-drain collector that requires a 1 k pull-up resistor. A write or read access occurs when the SDA line is pulled low while the SCL line is high, indicated by START in the timing diagrams. SDA is allowed to change only when SCL is low, except when a start or stop condition occurs, as shown in Figure 53 and Figure 54. The I2C interface supports both standard (100 kbps) and fast (400 kbps) modes as defined by the I2C standards. The first eight bits of the access consist of the device address and the R/W bit. The device address consists of an internal built-in address (0b00100) and two address pins, AD1 and AD0. The two address pins allow up to four ADAV803s to be used in a system.
SCK
SDA START BY MASTER
0
0
1
0
0
AD1
AD0
R/W
1 ACK. BY ADAV803
1
0
1
0
0
0
X ACK. BY ADAV803
FRAME 1 CHIP ADDRESS BYTE
FRAME 2 REGISTER ADDRESS BYTE
SCK (CONTINUED) SDA (CONTINUED)
D7
D6
D5
D4
D3
D2
D1
D0
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FRAME 3 DATA BYTE TO ADAV803
ACK. BY ADAV803
STOP BY MASTER
Figure 53. Writing to the DAC Left Volume Register in I2C
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ADAV803
SCL
SDA START BY MASTER
0
0
1
0
0
AD1
AD0
R/W
1 ACK. BY ADAV803
1
0
1
0
0
0
X ACK. BY ADAV803
FRAME 1 CHIP ADDRESS BYTE
FRAME 2 REGISTER ADDRESS BYTE
SCL (CONTINUED) SDA (CONTINUED)
0
0
1
0
0
AD1
AD0
R/W
D7 ACK. BY ADAV803
D6
D5
D4
D3
D2
D1
D0
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REPEATED START BY MASTER
FRAME 3 CHIP ADDRESS BYTE
FRAME 4 REGISTER DATA
ACK. BY ADAV803
STOP BY MASTER
Figure 54. Reading from the DAC Left Volume Register in I2C
BLOCK READS AND WRITES
The ADAV803 provides the user with the ability to write to or read from a block of registers in one continuous operation. To use this feature, the user has to continue providing data frames before the stop condition. For a write operation, the register address is automatically incremented with each additional frame and the register data is written to that register address. For a read operation, the register address is automatically incremented with each additional frame, and the register data is clocked out on that frame.
Care should be exercised when using the block read or block write modes. For most cases, block reading or writing to a register automatically increments the register address to point to the next register. The exceptions to this case are the indirect memory address registers, transmitter user bit and receiver user bit data buffers. Using a block read or write to access these registers does not update the absolute register address, but instead updates the buffer address to provide the next value in the buffer.
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ADAV803 REGISTER DESCRIPTIONS
Table 17. SRC and Clock Control Register
SRCDIV1 SRCDIV0 CLK2DIV1 7 6 5 ADDRESS = 0000000 (0x00) Divides the SRC master clock. SRCDIV1-0 00 = SRC master clock is not divided. 01 = SRC master clock is divided by 1.5. 10 = SRC master clock is divided by 2. 11= SRC master clock is divided by 3. Clock divider for Internal Clock 2 (ICLK2). CLK2DIV1-0 00 = Divide by 1. 01 = Divide by 1.5. 10 = Divide by 2. 11 = Divide by 3. Clock divider for Internal Clock 1 (ICLK1). CLK1DIV1-0 00 = Divide by 1. 01 = Divide by 1.5. 10 = Divide by 2. 11 = Divide by 3. Clock selection for the SRC master clock. MCLKSEL1-0 00 = Internal Clock 1. 01 = Internal Clock 2. 10 = PLL recovered clock (512 x fS). 11 = PLL recovered clock (256 x fS). CLK2DIV0 4 CLK1DIV1 3 CLK1DIV0 2 MCLKSEL1 1 MCLKSEL0 0
Table 18. SPDIF Loopback Control Register
RES RES RES RES 7 6 5 4 ADDRESS = 0000011 (0x03) Selects the source for SPDIF output (DITOUT). TxMUX 0 = SPDIF transmitter, normal mode. 1 = DIRIN, loopback mode. RES 3 RES 2 RES 1 TxMUX 0
Table 19. Playback Port Control Register
RES RES RES CLKSRC1 CLKSRC0 7 6 5 4 3 ADDRESS = 0000100 (0x04) Selects the clock source for generating the ILRCLK and IBCLK. CLKSRC1-0 00 = Input port is a slave. 01 = Recovered PLL clock. 10 = Internal Clock 1. 11 = Internal Clock 2. Selects the serial format of the playback port. SPMODE2-0 000 = Left-justified. 001 = I2S. 100 = 24-bit, right-justified. 101 = 20-bit, right-justified. 110 = 18-bit, right-justified. 111 = 16-bit, right-justified. SPMODE2 2 SPMODE1 1 SPMODE0 0
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ADAV803
Table 20. Auxiliary Input Port Register
RES RES RES CLKSRC1 CLKSRC0 7 6 5 4 3 ADDRESS = 0000101 (0x05) Selects the clock source for generating the IAUXLRCLK and IAUXBCLK. CLKSRC1-0 00 = Input port is a slave. 01 = Recovered PLL cock. 10 = Internal Clock 1. 11 = Internal Clock 2. Selects the serial format of auxiliary input port. SPMODE2-0 000 = Left-justified. 001 = I2S. 100 = 24-bit, right-justified. 101 = 20-bit, right-justified. 110 = 18-bit, right-justified. 111 = 16-bit, right-justified. SPMODE2 2 SPMODE1 1 SPMODE0 0
Table 21. Record Port Control Register
RES RES CLKSRC1 CLKSRC0 WLEN1 7 6 5 4 3 ADDRESS = 0000110 (0x06) Selects the clock source for generating the OLRCLK and OBCLK. CLKSRC1-0 00 = Record port is a slave. 01 = Recovered PLL clock. 10 = Internal Clock 1. 11 = Internal Clock 2. Selects the serial output word length. WLEN1-0 00 = 24 bits. 01 = 20 bits. 10 = 18 bits. 11 = 16 bits. Selects the serial format of the record port. SPMODE1-0 00 = Left-justified. 01 = I2S. 10 = Reserved. 11 = Right-justified. WLEN0 2 SPMODE1 1 SPMODE0 0
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ADAV803
Table 22. Auxiliary Output Port Register
RES RES CLKSRC1 CLKSRC0 WLEN1 7 6 5 4 3 ADDRESS = 0000111 (0x07) Selects the clock source for generating the OAUXLRCLK and OAUXBCLK. CLKSRC1-0 00 = Auxiliary record port is a slave. 01 = Recovered PLL clock. 10 = Internal Clock 1. 11 = Internal Clock 2. Selects the serial output word length. WLEN1-0 00 = 24 bits. 01 = 20 bits. 10 = 18 bits. 11 = 16 bits. Selects the serial format of the auxiliary record port. SPMODE1-0 00 = Left-justified. 01 = I2S. 10 = Reserved. 11 = Right-justified. WLEN0 2 SPMODE1 1 SPMODE0 0
Table 23. Group Delay and Mute Register
MUTE_SRC GRPDLY6-0 7 6, 5, 4, 3, 2, 1, 0 ADDRESS = 0001000 (0x08) Soft-mutes the output of the sample rate converter. MUTE_SRC 0 = No mute. 1 = Soft-mute. GRPDLY6-0 Adds delay to the sample rate converter FIR filter by GRPDLY6-0 input samples. 0000000 = No delay. 0000001 = 1 sample delay. 0000010 = 2 sample delay. 1111110 = 126 sample delay. 1111111 = 127 sample delay.
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ADAV803
Table 24. Receiver Configuration 1 Register
NOCLOCK RxCLK1-0 AUTO_ DEEMPH ERR1-0 LOCK1-0 7 6, 5 4 3, 2 1, 0 ADDRESS = 0001001 (0x09) Selects the source of the receiver clock when the PLL is not locked. NOCLOCK 0 = Recovered PLL clock is used. 1 = ICLK1 is used. Determines the oversampling ratio of the recovered receiver clock. RxCLK1-0 00 = RxCLK is a 128 x fS recovered clock. 01 = RxCLK is a 256 x fS recovered clock. 10 = RxCLK is a 512 x fS recovered clock. 11 = Reserved. Automatically de-emphasizes the data from the receiver based on the channel status information. AUTO_DEEMPH 0 = Automatic de-emphasis is disabled. 1 = Automatic de-emphasis is enabled. Defines what action the receiver should take, if the receiver detects a parity or biphase error. ERR1-0 00 = No action is taken. 01 = Last valid sample is held. 10 = Invalid sample is replaced with zeros. 11 = Reserved. Defines what action the receiver should take, if the PLL loses lock. LOCK1-0 00 = No action is taken. 01 = Last valid sample is held. 10 = Zeros are sent out after the last valid sample. 11 = Soft-mute of the last valid audio sample.
Table 25. Receiver Configuration 2 Register
RxMUTE SP_PLL SP_PLL_ SEL1-0 RES RES NO NONAUDIO NO_VALIDITY 7 6 5, 4 3 2 1 0 ADDRESS = 0001010 (0x0A) Hard-mutes the audio output for the AES3/SPDIF receiver. RxMUTE 0 = AES3/SPDIF receiver is not muted. 1 = AES3/SPDIF receiver is muted. AES3/SPDIF receiver PLL accepts a left/right clock from one of the four serial ports as the PLL reference clock. SP_PLL 0 = Left/right clock generated from the AES3/SPDIF preambles is the reference clock to the PLL. 1 = Left/right clock from one of the serial ports is the reference clock to the PLL. Selects one of the four serial ports as the reference clock to the PLL when SP_PLL is set. SP_PLL_SEL1-0 00 = Playback port is selected. 01 = Auxiliary input port is selected. 10 = Record port is selected. 11 = Auxiliary output port is selected. When the NONAUDIO bit is set, data from the AES3/SPDIF receiver is not allowed into the sample rate converter NO NONAUDIO (SRC). If the NONAUDIO data is due to DTS, AAC, and so on, as defined by the IEC61937 standard, then the data from the AES3/SPDIF receiver is not allowed into the SRC regardless of the state of this bit. 0 = AES3/SPDIF receiver data is sent to the SRC. 1 = Data from the AES3/SPDIF receiver is not allowed into the SRC, if the NONAUDIO bit is set. When the VALIDITY bit is set, data from the AES3/SPDIF receiver is not allowed into the SRC. NO_VALIDITY 0 = AES3/SPDIF receiver data is sent to the SRC. 1 = Data from the AES3/SPDIF receiver is not allowed into the SRC, if the VALIDITY bit is set.
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ADAV803
Table 26. Receiver Buffer Configuration Register
RES RES RxBCONF5 RxBCONF4 RxBCONF3 RxBCONF2-1 RxBCONF0 7 6 5 4 3 2, 1 0 ADDRESS = 0001011 (0x0B) If the user bits are formatted according to the IEC60958-3 standard and the DAT category is detected, the user bit RxBCONF5 interrupt is enabled only when there is a change in the start (ID) bit. 0 = User bit interrupt is enabled in normal mode. 1 = If the DAT category is detected, the user bit interrupt is enabled only if there is a change in the start (ID) bit. This bit determines whether Channel A and Channel B user bits are stored in the buffer together or separated RxBCONF4 between A and B. 0 = User bits are stored together. 1 = User bits are stored separately. Defines the function of RxCSBINT. RxBCONF3 0 = RxCSBINT are set when a new block of receiver channel status is read, which is 192 audio frames. 1 = RxCSBINT is set only if the first five bytes of the receiver channel status block changes from the previous channel status block. Defines the user bit buffer. RxBCONF2-1 00 = User bits are ignored. 01 = Updates the second user bit buffer when the first user bit buffer is full. 10 = Formats the received user bits according to Byte 1, Bit 4 to Bit 7, of the channel status, if the PRO bit is set. If the PRO bit is not set, formats the user bits according to the IEC60958-3 standard. 11 = Reserved. Defines the user bit buffer size, if RxBCONF2-1 = 01. RxBCONF0 0 = 384 bits with Preamble Z as the start of the buffer. 1 = 768 bits with Preamble Z as the start of the buffer.
Table 27. Transmitter Control Register
RES TxVALIDITY TxRATIO2-0 TxCLKSEL1-0 7 6 5, 4, 3 2, 1 ADDRESS = 0001100 (0x0C) This bit is used to set or clear the VALIDITY bit in the AES3/SPDIF transmit stream. TxVALIDITY 0 = Audio is suitable for D/A conversion. 1 = Audio is not suitable for D/A conversion. Determines the AES3/SPDIF transmitter to AES3/SPDIF receiver ratio. TxRATIO2-0 000 = Transmitter to receiver ratio is 1:1. 001 = Transmitter to receiver ratio is 1:2. 010 = Transmitter to receiver ratio is 1:4. 101 = Transmitter to receiver ratio is 2:1. 110 = Transmitter to receiver ratio is 4:1. Selects the clock source for the AES3/SPDIF transmitter. TxCLKSEL1-0 00 = Internal Clock 1 is the clock source for the transmitter. 01 = Internal Clock 2 is the clock source for the transmitter. 10 = Recovered PLL clock is the clock source for the transmitter. 11 = Reserved. Enables the AES3/SPDIF transmitter. TxENABLE 0 = AES3/SPDIF transmitter is disabled. 1 = AES3/SPDIF transmitter is enabled. TxENABLE 0
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Table 28. Transmitter Buffer Configuration Register
IU_Zeros3-0 TxBCONF3 TxBCONF2-1 TxBCONF0 7, 6, 5, 4 3 2, 1 0 ADDRESS = 0001101 (0x0D) Determines the number of zeros to be stuffed between IUs in a message up to a maximum of 8. IU_Zeros3-0 0000 = 0. 0001 = 1. ... 0111 = 7. 1000 = 8. Transmitter user bits can be stored in separate buffers or stored together. TxBCONF3 0 = User bits are stored together. 1 = User bits are stored separately. Configures the transmitter user bit buffer. TxBCONF2-1 00 = Zeros are transmitted for the user bits. 01 = Transmitter user bit buffer size is configured according to TxBCONF0. 10 = User bits are written to the transmit buffer in IUs specified by the IEC60958-3 standard. 11 = Reserved. TxBCONF0 Determines the buffer size of the transmitter user bits when TxBCONF2-1 is 01. 0 = 384 bits with Preamble Z as the start of the buffer. 1 = 768 bits with Preamble Z as the start of the buffer.
Table 29. Channel Status Switch Buffer and Transmitter
RES RES Tx_A/B_Same Disable_Tx_Copy RES RES TxCSSWITCH RxCSSWITCH 7 6 5 4 3 2 1 0 ADDRESS = 0001110 (0x0E) Transmitter Channel Status A and B are the same. The transmitter reads only from the Channel Status A buffer and Tx_A/B_Same places the data into the Channel Status B buffer. 0 = Channel status for A and B are separate. 1 = Channel status for A and B are the same. Disables the copying of the channel status bits from the transmitter channel status buffer to the SPDIF transmitter Disable_Tx_Copy buffer. 0 = Copying transmitter channel status is enabled. 1 = Copying transmitter channel status is disabled. Toggle switch for the transmit channel status buffer. TxCSSWITCH 0 = 24-byte Transmitter Channel Status A buffer can be accessed at address locations 0x38 through 0x4F. 1 = 24-byte Transmitter Channel Status B buffer can be accessed at address locations 0x38 through 0x4F. Toggle switch for the receive channel status buffer. RxCSSWITCH 0 = 24-byte Receiver Channel Status A buffer can be accessed at address locations 0x20 through 0x37. 1 = 24-byte Receiver Channel Status B buffer can be accessed at address locations 0x20 through 0x37.
Table 30. Transmitter Message Zeros Most Significant Byte
MSBZeros7-0 7, 6, 5, 4, 3, 2, 1, 0 ADDRESS = 0001111 (0x0F) Most significant byte of the number of zeros to be stuffed between IEC60958-3 messages (packets). MSBZeros7-0 Default = 0x00.
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Table 31. Transmitter Message Zeros Least Significant Byte
LSBZeros7-0 7, 6, 5, 4, 3, 2, 1, 0 ADDRESS = 0010000 (0x10) Least significant byte of the number of zeros to be stuffed between IEC60958-3 messages (packets). Default = 0x09. LSBZeros7-0
Table 32. Autobuffer Register
RES Zero_Stuff_IU Auto_UBits Auto_CSBits IU_Zeros3-0 7 6 5 4 3, 2, 1, 0 ADDRESS = 0010001 (0x11) Enables the addition or subtraction of zeros between IUs during autobuffering of the user bits in IEC60958-3 format. Zero_Stuff_IU 0 = No zeros added or subtracted. 1 = Zeros can be added or subtracted between IUs. Enables the user bits to be autobuffered between the AES3/SPDIF receiver and transmitter. Auto_UBits 0 = User bits are not autobuffered. 1 = User bits are autobuffered. Enables the channel status bits to be autobuffered between the AES3/SPDIF receiver and transmitter. Auto_CSBits 0 = Channel status bits are not autobuffered. 1 = Channel status bits are autobuffered. Sets the maximum number of zero-stuffing to be added between IUs while autobuffering up to a maximum of 8. IU_Zeros3-0 0000 = 0. 0001 = 1. ... 0111 = 7. 1000 = 8.
Table 33. Sample Rate Ratio MSB Register (Read Only)
RES SRCRATIO14-SRCRATIO08 7 6, 5, 4, 3, 2, 1, 0 ADDRESS = 0010010 (0x12) Seven most significant bits of the15-bit sample rate ratio. SRCRATIO14-08
Table 34. Sample Rate Ratio LSB Register (Read Only)
SRCRATIO07-SRCRATIO00 7, 6, 5, 4, 3, 2, 1, 0 ADDRESS = 0010011 (0x13) Eight least significant bits of the15-bit sample rate ratio. SRCRATIO07-00
Table 35. Preamble-C MSB Register (Read Only)
PRE_C15-PRE_C08 7, 6, 5, 4, 3, 2, 1, 0 ADDRESS = 0010100 (0x14) Eight most significant bits of the 16-bit Preamble-C, when nonaudio data is detected according to the IEC60937 PRE_C15-08 standard; otherwise, bits show zeros.
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Table 36. Preamble-C LSB Register (Read Only)
PRE_C07-PRE_C00 7, 6, 5, 4, 3, 2, 1, 0 ADDRESS = 0010101 (0x15) Eight least significant bits of the 16-bit Preamble-C, when nonaudio data is detected according to the IEC60937 PRE_C07-00 standard; otherwise, bits show zeros.
Table 37. Preamble-D MSB Register (Read Only)
PRE_D15-PRE_D08 7, 6, 5, 4, 3, 2, 1, 0 ADDRESS = 0010110 (0x16) Eight most significant bits of the 16-bit Preamble-D, when nonaudio data is detected according to the IEC60937 PRE_D15-08 standard; otherwise, bits show zeros. When subframe nonaudio is used, this becomes the eight most significant bits of the 16-bit Preamble-C of Channel B.
Table 38. Preamble-D LSB Register (Read Only)
PRE_D07-PRE_D00 7, 6, 5, 4, 3, 2, 1, 0 ADDRESS = 0010111 (0x17) Eight least significant bits of the 16-bit Preamble-D, when nonaudio data is detected according to the IEC60937 PRE_D07-00 standard; otherwise, bits show zeros. When subframe nonaudio is used, this becomes the eight most significant bits of the 16-bit Preamble-C of Channel B.
Table 39. Receiver Error Register (Read Only)
NonAudio Preamble RxValidity Emphasis NonAudio CRCError NoStream BiPhase/ Parity Lock 7 6 5 4 3 2 1 0 ADDRESS = 0011000 (0x18) This is the VALIDITY bit in the AES3 received stream. RxValidity This bit is set, if the audio data is pre-emphasized. Once it has been read, it remains high and does not generate an Emphasis interrupt unless it changes state. This bit is set, when Channel Status Bit 1 (nonaudio) is set. Once it has been read, it does not generate another NonAudio interrupt unless the data becomes audio or the type of nonaudio data changes. This bit is set, if the audio data is nonaudio due to the detection of a preamble. The nonaudio preamble type register NonAudio indicates what type of preamble was detected. Once read, it remains in its state and does not generate an interrupt Preamble unless it changes state. This bit is the error flag for the channel status CRCError check. This bit does not clear until the receiver error register CRCError is read. This bit is set, if there is no AES3/SPDIF stream present at the AES3/SPDIF receiver. Once read, it remains high and NoStream does not generate an interrupt unless it changes state. This bit is set, if a biphase or parity error occurred in the AES3/SPDIF stream. This bit is not cleared until the register is BiPhase/Parity read. This bit is set, if the PLL has locked or cleared when the PLL loses lock. Once read, it remains in its state and does not Lock generate an interrupt unless it changes state.
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Table 40. Receiver Error Mask Register
NonAudio RxValidity Emphasis NonAudio CRCError Preamble Mask Mask Mask Mask Mask 7 6 5 4 3 ADDRESS = 0011001 (0x19) Masks the RxValidity bit from generating an interrupt. RxValidity Mask 0 = RxValidity bit does not generate an interrupt. 1 = RxValidity bit generates an interrupt. Masks the emphasis bit from generating an interrupt. Emphasis Mask 0 = Emphasis bit does not generate an interrupt. 1 = Emphasis bit generates an interrupt. Masks the NonAudio bit from generating an interrupt. NonAudio Mask 0 = NonAudio bit does not generate an interrupt. 1 = NonAudio bit generates an interrupt. Masks the NonAudio preamble bit from generating an interrupt. NonAudio Preamble Mask 0 = NonAudio preamble bit does not generate an interrupt. 1 = NonAudio preamble bit generates an interrupt. Masks the CRCError bit from generating an interrupt. CRCError Mask 0 = CRCError bit does not generate an interrupt. 1 = CRCError bit generates an interrupt. Masks the NoStream bit from generating an interrupt. NoStream Mask 0 = NoStream bit does not generate an interrupt. 1 = NoStream bit generates an interrupt. Masks the BiPhase/Parity bit from generating an interrupt. BiPhase/Parity Mask 0 = BiPhase/Parity bit does not generate an interrupt. 1 = BiPhase/Parity bit generates an interrupt. Masks the Lock bit from generating an interrupt. Lock Mask 0 = Lock bit does not generate an interrupt. 1 = Lock bit generates an interrupt. NoStream Mask 2 BiPhase/ Parity Mask 1
Lock Mask 0
Table 41. Sample Rate Converter Error Register (Read Only)
RES RES RES RES TOO_SLOW OVRL OVRR MUTE_IND 7 6 5 4 3 2 1 0 ADDRESS = 0011010 (0x1A) This bit is set, when the clock to the SRC is too slow, that is, there are not enough clock cycles to complete the TOO_SLOW internal convolution. This bit is set, when the left output data of the sample rate converter has gone over the full-scale range and has been OVRL clipped. This bit is not cleared until the register is read. This bit is set, when the right output data of the sample rate converter has gone over the full-scale range and has OVRR been clipped. This bit is not cleared until the register is read. Mute indicated. This bit is set, when the SRC is in fast mode and clicks or pops can be heard in the SRC output data. MUTE_IND The output of the SRC can be muted, if required, until the SRC is in slow mode. Once read, this bit remains in its state and does not generate an interrupt until it has changed state.
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Table 42. Sample Rate Converter Error Mask Register
RES RES RES RES RES OVRL Mask 7 6 5 4 3 2 ADDRESS = 0011011 (0x1B) Masks the OVRL from generating an interrupt. OVRL Mask 0 = OVRL bit does not generate an interrupt. 1 = OVRL bit generates an interrupt. Masks the OVRR from generating an interrupt. OVRR Mask 0 = OVRR bit does not generate an interrupt. 1 = OVRR bit generates an interrupt. Reserved. Masks the MUTE_IND from generating an interrupt. MUTE_IND MASK 0 = MUTE_IND bit does not generate an interrupt. 1 = MUTE_IND bit generates an interrupt. OVRR Mask 1 MUTE_IND MASK 0
Table 43. Interrupt Status Register
SRCError TxCSTINT TxUBINT TxCSINT RxCSDIFF RxUBINT RxCSBINT RxERROR 7 6 5 4 3 2 1 0 ADDRESS = 0011100 (0x1C) This bit is set, if one of the sample rate converter interrupts is asserted, and the host should immediately read the SRCError sample rate converter error register. This bit remains high until the interrupt status register is read. This bit is set, if a write to the transmitter channel status buffer was made while transmitter channel status bits were TxCSTINT being copied from the transmitter CS buffer to the SPDIF transmit buffer. This bit is set, if the SPDIF transmit buffer is empty. This bit remains high until the interrupt status register is read. TxUBINT This bit is set, if the transmitter channel status bit buffer has transmitted its block of channel status. This bit remains TxCSINT high until the interrupt status register is read. This bit is set, if the receiver Channel Status A block is different from the receiver Channel Status B clock. This bit RxCSDIFF remains high until read, but does not generate an interrupt. This bit is set, if the receiver user bit buffer has a new block or message. This bit remains high until the interrupt RxUBINT status register is read. This bit is set, if a new block of channel status is read when RxBCONF3 = 0, or if the channel status has changed when RxCSBINT RxBCONF3 = 1. This bit remains high until the interrupt status register is read. This bit is set, if one of the AES3/SPDIF receiver interrupts is asserted, and the host should immediately read the RxERROR receiver error register. This bit remains high until the interrupt status register is read.
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Table 44. Interrupt Status Mask Register
SRCError TxCSTINT TxUBINT TxCSBINT Mask Mask Mask Mask 7 6 5 4 ADDRESS = 0011101 (0x1D) Masks the SRCError bit from generating an interrupt. SRCError Mask 0 = SRCError bit does not generate an interrupt. 1 = SRCError bit generates an interrupt. Masks the TxCSTINT bit from generating an interrupt. TxCSTINT Mask 0 = TxCSTINT bit does not generate an interrupt. 1 = TxCSTINT bit generates an interrupt. Masks the TxUBINT bit from generating an interrupt. TxUBINT Mask 0 = TxUBINT bit does not generate an interrupt. 1 = TxUBINT bit generates an interrupt. Masks the TxCSBINT bit from generating an interrupt. TxCSBINT Mask 0 = TxCSBINT bit does not generate an interrupt. 1 = TxCSBINT bit generates an interrupt. Masks the RxUBINT bit from generating an interrupt. RxUBINT Mask 0 = RxUBINT bit does not generate an interrupt. 1 = RxUBINT bit generates an interrupt. Masks the RxCSBINT bit from generating an interrupt. RxCSBINT Mask 0 = RxCSBINT bit does not generate an interrupt. 1 = RxCSBINT bit generates an interrupt. Masks the RxError bit from generating an interrupt. RxError Mask 0 = RxError bit does not generate an interrupt. 1 = RxError bit generates an interrupt. RES 3 RxUBINT Mask 2 RxCSBINT Mask 1 RxError Mask 0
Table 45. Mute and De-Emphasis Register
RES RES TxMUTE RES RES 7 6 5 4 3 ADDRESS = 0011110 (0x1E) Mutes the AES3/SPDIF transmitter. TxMUTE 0 = Transmitter is not muted. 1 = Transmitter is muted. Selects the de-emphasis filter for the input data to the sample rate converter. SRC_DEEM1-0 00 = No de-emphasis. 01 = 32 kHz de-emphasis. 10 = 44.1 kHz de-emphasis. 11 = 48 kHz de-emphasis. SRC_DEEM1-0 2, 1 RES 0
Table 46. NonAudio Preamble Type Register (Read Only)
DTS-CD NonAudio NonAudio NonAudio RES RES RES RES Preamble Frame Subframe_A Subframe_B 7 6 5 4 3 2 1 0 ADDRESS = 0011111 (0x1F) This bit is set, if the DTS-CD preamble is detected. DTS-CD Preamble This bit is set, if the data received through the AES3/SPDIF receiver is nonaudio data according to the IEC61937 NonAudio Frame standard or nonaudio data according to SMPTE337M. This bit is set, if the data received through Channel A of the AES3/SPDIF receiver is subframe nonaudio data NonAudio according to SMPTE337M. Subframe_A This bit is set, if the data received through Channel B of the AES3/SPDIF receiver is subframe nonaudio data NonAudio according to SMPTE337M. Subframe_B
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Table 47. Receiver Channel Status Buffer
RCSB7-RCSB0 7, 6, 5, 4, 3, 2, 1, 0 ADDRESS = 0100000 to 0110111 (0x20 to 0x37) The 24-byte receiver channel status buffer. The PRO bit is stored at address location 0x20, Bit 0. This buffer is read RCSB7-0 only if the channel status is not autobuffered between the receiver and transmitter.
Table 48. Transmitter Channel Status Buffer
TCSB7-TCSB0 7, 6, 5, 4, 3, 2, 1, 0 ADDRESS = 0111000 to 1001111 (0x38 to 0x4F) The 24-byte transmitter channel status buffer. The PRO bit is stored at address location 0x38, Bit 0. This buffer is TCSB7-0 disabled when autobuffering between the receiver and transmitter is enabled.
Table 49. Receiver User Bit Buffer Indirect Address Register
RxUBADDR07-RxUBADDR00 7, 6, 5, 4, 3, 2, 1, 0 ADDRESS = 1010000 (0x50) Indirect address pointing to the address location in the receiver user bit buffer. RxUBADDR07-00
Table 50. Receiver User Bit Buffer Data Register
RxUBDATA07-RxUBDATA00 7, 6, 5, 4, 3, 2, 1, 0 ADDRESS = 1010001 (0x51) A read from this register reads eight bits of user data from the receiver user bit buffer pointed to by RxUBADDR07- RxUBDATA07-00 00. This buffer can be written to when autobuffering of the user bits is enabled; otherwise, it is a read-only buffer.
Table 51. Transmitter User Bit Buffer Indirect Address Register
TxUBADDR07-TxUBADDR00 7, 6, 5, 4, 3, 2, 1, 0 ADDRESS = 1010010 (0x52) Indirect address pointing to the address location in the transmitter user bit buffer. TxUBADDR07-00
Table 52. Transmitter User Bit Buffer Data Register
TxUBDATA07-TxUBDATA00 7, 6, 5, 4, 3, 2, 1, 0 ADDRESS = 1010011 (0x53) A write to this register writes eight bits of user data to the transmit user bit buffer pointed to by TxUBADDR07-00. TxUBDATA07-00 When user bit autobuffering is enabled, this buffer is disabled.
Table 53. Q Subcode CRCError Status Register (Read-Only)
RES RES RES RES RES RES QCRCERROR QSUB 7 6 5 4 3 2 1 0 ADDRESS = 1010100 (0x54) This bit is set, if the CRC check of the Q subcode fails. This bit remains high, but does not generate an interrupt. This QCRCERROR bit is cleared once the register is read. This bit is set, if a Q subcode has been read into the Q subcode buffer (see Table 54). QSUB
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Table 54. Q Subcode Buffer
Address 0x55 0x56 0x57 0x58 0x59 0x5A 0x5B 0x5C 0x5D 0x5E Bit 7 Address Track number Index Minute Second Frame Zero Absolute minute Absolute second Absolute frame Bit 6 Address Track number Index Minute Second Frame Zero Absolute minute Absolute second Absolute frame Bit 5 Address Track number Index Minute Second Frame Zero Absolute minute Absolute second Absolute frame Bit 4 Address Track number Index Minute Second Frame Zero Absolute minute Absolute second Absolute frame Bit 3 Control Track number Index Minute Second Frame Zero Absolute minute Absolute second Absolute frame Bit 2 Control Track number Index Minute Second Frame Zero Absolute minute Absolute second Absolute frame Bit 1 Control Track number Index Minute Second Frame Zero Absolute minute Absolute second Absolute frame Bit 0 Control Track number Index Minute Second Frame Zero Absolute minute Absolute second Absolute frame
Table 55. Datapath Control Register 1
SRC1 SRC0 REC2 REC1 7 6 5 4 ADDRESS = 1100010 (0x62) Datapath source select for sample rate converter (SRC). SRC1-0 00 = ADC. 01 = DIR. 10 = Playback. 11 = Auxiliary in. Datapath source select for record output port. REC2-0 000 = ADC. 001 = DIR. 010 = Playback. 011 = Auxiliary in. 100 = SRC. Datapath source select for auxiliary output port. AUXO2-0 000 = ADC. 001 = DIR. 010 = Playback. 011 = Auxiliary in. 100 = SRC. REC0 3 AUXO2 2 AUXO1 1 AUXO0 0
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Table 56. Datapath Control Register 2
RES RES DAC2 7 6 5 ADDRESS = 1100011 (0x63) Datapath source select for DAC. DAC2-0 00 = ADC. 01 = DIR. 10 = Playback. 11 = Auxiliary in. 100 = SRC. Datapath source select for DIT. DIT2-0 000 = ADC. 001 = DIR. 010 = Playback. 011 = Auxiliary in. 100 = SRC. DAC1 4 DAC0 3 DIT2 2 DIT1 1 DIT0 0
Table 57. DAC Control Register 1
DR_ALL DR_DIG CHSEL1 CHSEL0 7 6 5 4 ADDRESS = 1100100 (0x64) Hard reset and power-down. DR_ALL 0 = Normal, output pins go to VREF level. 1 = Hard reset and low power, output pins go to AGND. DR_DIG DAC digital reset. 0 = Normal. 1 = Reset all except registers. DAC channel select. 00 = Normal, left-right. 01 = Both right. 10 = Both left. 11 = Swapped, right-left. DAC channel polarity. 00 = Both positive. 01 = Left negative. 10 = Right negative. 11 = Both negative. Mute right channel. 0 = Normal. 1 = Mute. Mute left channel. 0 = Normal. 1 = Mute. POL1 3 POL0 2 MUTER 1 MUTEL 0
CHSEL1-0
POL1-0
MUTER
MUTEL
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Table 58. DAC Control Register 2
RES RES 7 6 ADDRESS = 1100101 (0x65) DAC MCLK divider. DMCLK1-0 00 = MCLK. 01 = MCLK/1.5. 10 = MCLK/2. 11 = MCLK/3. DAC interpolator select. DFS1-0 00 = 8 x (MCLK = 256 x fS). 01 = 4 x (MCLK = 128 x fS). 10 = 2 x (MCLK = 64 x fS). 11 = Reserved. DAC de-emphasis select. DEEM1-0 00 = None. 01 = 44.1 kHz. 10 = 32 kHz. 11 = 48 kHz. DMCLK1 5 DMCLK0 4 DFS1 3 DFS0 2 DEEM1 1 DEEM0 0
Table 59. DAC Control Register 3
RES RES RES 7 6 5 ADDRESS = 1100110 (0x66) DAC zero flag on mute and zero volume. ZFVOL 0 = Enabled. 1 = Disabled. DAC zero flag on zero data disable. ZFDATA 0 = Enabled. 1 = Disabled. DAC zero flag polarity. ZFPOL 0 = Active high. 1 = Active low. RES 4 RES 3 ZFVOL 2 ZFDATA 1 ZFPOL 0
Table 60. DAC Control Register 4
RES INTRPT ZEROSEL1 ZEROSEL0 RES RES RES 7 6 5 4 3 2 1 ADDRESS = 1100111 (0x67) This bit selects the functionality of the ZEROL/INT pin. INTRPT 0 = Pin functions as a ZEROL flag pin. 1 = Pin functions as an interrupt pin. These bits control the functionality of the ZEROR pin when the ZEROL/INT pin is used as an interrupt. ZEROSEL1-0 00 = Pin functions as a ZEROR flag pin. 01 = Pin functions as a ZEROL flag pin. 10 = Pin is asserted when either the left or right channel is zero. 11 = Pin is asserted when both the left and right channels are zero. RES 0
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Table 61. DAC Left Volume Register
DVOLL7 DVOLL6 DVOLL5 7 6 5 ADDRESS = 1101000 (0x68) DAC left channel volume control. DVOLL7-0 1111111 = 0 dBFS. 1111110 = -0.375 dBFS. 0000000 = -95.625 dBFS. DVOLL4 4 DVOLL3 3 DVOLL2 2 DVOLL1 1 DVOLL0 0
Table 62. DAC Right Volume Register
DVOLR7 DVOLR6 DVOLR5 7 6 5 ADDRESS = 1101001 (0x69) DAC right channel volume control. DVOLR7-0 1111111 = 0 dBFS. 1111110 = -0.375 dBFS. 0000000 = -95.625 dBFS. DVOLR4 4 DVOLR3 3 DVOLR2 2 DVOLR1 1 DVOLR0 0
Table 63. DAC Left Peak Volume Register
RES RES DLP5 7 6 5 ADDRESS = 1101010 (0x6A) DAC left channel peak volume detection. DLP5-0 000000 = 0 dBFS. 000001 = -1 dBFS. 111111 = -63 dBFS. DLP4 4 DLP3 3 DLP2 2 DLP1 1 DLP0 0
Table 64. DAC Right Peak Volume Register
RES RES DRP5 DRP4 7 6 5 4 ADDRESS = 1101011 (0x6B) DAC right channel peak volume detection. DRP5-0 000000 = 0 dBFS. 000001 = -1 dBFS. 111111 = -63 dBFS. DRP3 3 DRP2 2 DRP1 1 DRP0 0
Table 65. ADC Left Channel PGA Gain Register
RES RES AGL5 7 6 5 ADDRESS = 1101100 (0x6C) PGA left channel gain control. AGL5-0 000000 = 0 dB. 000001 = 0.5 dB. ... 101111 = 23.5 dB. 110000 = 24 dB. ... 111111 = 24 dB. AGL4 4 AGL3 3 AGL2 2 AGL1 1 AGL0 0
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Table 66. ADC Right Channel PGA Gain Register
RES RES AGR5 7 6 5 ADDRESS = 1101101 (0x6D) PGA right channel gain control. AGR5-0 000000 = 0 dB. 000001 = 0.5 dB. ... 101111 = 23.5 dB. 110000 = 24 dB. ... 111111 = 24 dB. AGR4 4 AGR3 3 AGR2 2 AGR1 1 AGR0 0
Table 67. ADC Control Register 1
AMC HPF PWRDWN 7 6 5 ADDRESS = 1101110 (0x6E) ADC modulator clock. AMC 0 = ADC MCLK/2 (128 x fS). 1 = ADC MCLK/4 (64 x fS). High-pass filter enable. HPF 0 = Normal. 1 = HPF enabled. ADC power-down. PWRDWN 0 = Normal. 1 = Power-down. ADC analog section power-down. ANA_PD 0 = Normal. 1 = Power-down. Mute ADC right channel. MUTER 0 = Normal. 1 = Muted. Mute ADC left channel. MUTEL 0 = Normal. 1 = Muted. PGA left power-down. PLPD 0 = Normal. 1 = Power-down. PGA right power-down. PRPD 0 = Normal. 1 = Power-down. ANA_PD 4 MUTER 3 MUTEL 2 PLPD 1 PRPD 0
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Table 68. ADC Control Register 2
RES RES RES 7 6 5 ADDRESS = 1101111 (0x6F) Reference buffer power-down control. BUF_PD 0 = Normal. 1 = Power-down. ADC master clock divider. MCD1-0 00 = Divide by 1. 01 = Divide by 2. 10 = Divide by 3. 11 = Divide by 1. BUF_PD 4 RES 3 RES 2 MCD1 1 MCD0 0
Table 69. ADC Left Volume Register
AVOLL7 AVOLL6 AVOLL5 7 6 5 ADDRESS = 1110000 (0x70) ADC left channel volume control. AVOLL7-0 1111111 = 1.0 (0 dBFS). 1111110 = 0.996 (-0.00348 dBFS). 1000000 = 0.5 (-6 dBFS). 0111111 = 0.496 (-6.09 dBFS). 0000000 = 0.0039 (-48.18 dBFS). AVOLL4 4 AVOLL3 3 AVOLL2 2 AVOLL1 1 AVOLL0 0
Table 70. ADC Right Volume Register
AVOLR7 AVOLR6 AVOLR5 7 6 5 ADDRESS = 1110001 (0x71) ADC right channel volume control. AVOLR7-0 1111111 = 1.0 (0 dBFS). 1111110 = 0.996 (-0.00348 dBFS). 1000000 = 0.5 (-6 dBFS). 0111111 = 0.496 (-6.09 dBFS). 0000000 = 0.0039 (-48.18 dBFS). AVOLR4 4 AVOLR3 3 AVOLR2 2 AVOLR1 1 AVOLR0 0
Table 71. ADC Left Peak Volume Register
RES RES ALP5 7 6 5 ADDRESS = 1110010 (0x72) ADC left channel peak volume detection. ALP5-0 000000 = 0 dBFS. 000001 = -1 dBFS. 111111 = -63 dBFS. ALP4 4 ALP3 3 ALP2 2 ALP1 1 ALP0 0
Table 72. ADC Right Peak Volume Register
RES RES ARP5 ARP4 7 6 5 4 ADDRESS = 1110011 (0x73) ADC right channel peak volume detection. ARP5-0 000000 = 0 dBFS. 000001 = -1 dBFS. 111111 = -63 dBFS. ARP3 3 ARP2 2 ARP1 1 ARP0 0
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ADAV803
Table 73. PLL Control Register 1
DIRIN_CLK1 DIRIN_CLK0 MCLKODIV PLLDIV 7 6 5 4 ADDRESS = 1110100 (0x74) Recovered SPDIF clock sent to SYSCLK3. DIRIN_CLK1-0 00 = SYSCLK3 comes from PLL block. 01 = Reserved. 10 = Reserved. 11 = SYSCLK3 is the recovered SPDIF clock from DIRIN. Divide input MCLK by 2 to generate MCLKO. MCLKODIV 0 = Disabled. 1 = Enabled. Divide XIN by 2 to generate the PLL master clock. PLLDIV 0 = Disabled. 1 = Enabled. Power-down PLL2. PLL2PD 0 = Normal. 1 = Power-down. Power-down PLL1. PLL1PD 0 = Normal. 1 = Power-down. Power-down XTAL oscillator. XTLPD 0 = Normal. 1 = Power-down. Clock output for SYSCLK3. SYSCLK3 0 = 512 x fS. 1 = 256 x fS. PLL2PD 3 PLL1PD 2 XTLPD 1 SYSCLK3 0
Table 74. PLL Control Register 2
FS2_1 FS2_0 SEL2 7 6 5 ADDRESS = 1110101 (0x75) Sample rate select for PLL2. FS2_1-0 00 = 48 kHz. 01 = Reserved. 10 = 32 kHz. 11 = 44.1 kHz. Oversample ratio select for PLL2. SEL2 0 = 256 x fS. 1 = 384 x fS. Double-selected sample rate on PLL2. DOUB2 0 = Disabled. 1 = Enabled. Sample rate select for PLL1. FS1-0 00 = 48 kHz. 01 = Reserved. 10 = 32 kHz. 11 = 44.1 kHz. Oversample ratio select for PLL1. SEL1 0 = 256 x fS. 1 = 384 x fS. Double-selected sample rate on PLL1. DOUB1 0 = Disabled. 1 = Enabled. DOUB2 4 FS1 3 FS0 2 SEL1 1 DOUB1 0
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ADAV803
Table 75. Internal Clocking Control Register 1
DCLK2 DCLK1 DCLK0 7 6 5 ADDRESS = 1110110 (0x76) DAC clock source select. DCLK2-0 000 = XIN. 001 = MCLKI. 010 = PLLINT1. 011 = PLLINT2. 100 = DIR PLL (512 x fS). 101 = DIR PLL (256 x fS). 110 = XIN. 111 = XIN. ADC clock source select. ACLK2-0 000 = XIN. 001 = MCLKI. 010 = PLLINT1. 011 = PLLINT2. 100 = DIR PLL (512 x fS). 101 = DIR PLL (256 x fS). 110 = XIN. 111 = XIN. Source selector for internal clock ICLK2. ICLK2_1-0 00 = XIN. 01 = MCLKI. 10 = PLLINT1. 11 = PLLINT2. ACLK2 4 ACLK1 3 ACLK0 2 ICLK2_1 1 ICLK2_0 0
Table 76. Internal Clocking Control Register 2
RES RES RES 7 6 5 ADDRESS = 1110111 (0x77) Source selector for internal clock ICLK1. ICLK1_1-0 00 = XIN. 01 = MCLKI. 10 = PLLINT1. 11 = PLLINT2. PLL2 internal selector (see Figure 38). PLL2INT1-0 00 = FS2. 01 = FS2/2. 10 = FS3. 11 = FS3/2. PLL1 internal selector. PLL1INT 0 = FS1. 1 = FS1/2. ICLK1_1 4 ICLK1_0 3 PLL2INT1 2 PLL2INT0 1 PLL1INT 0
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ADAV803
Table 77. PLL Clock Source Register
PLL1_Source PLL2_Source RES 7 6 5 ADDRESS = 1111000 (0x78) Selects the clock source for PLL1. PLL1_Source 0 = XIN. 1 = MCLKI. Selects the clock source for PLL2. PLL2_Source 0 = XIN. 1 = MCLKI. RES 4 RES 3 RES 2 RES 1 RES 0
Table 78. PLL Output Enable Register
RES RES DIRINPD DIRIN_PIN RES SYSCLK1 7 6 5 4 3 2 ADDRESS = 1111010 (0x7A) This bit powers down the SPDIF receiver. DIRINPD 0 = Normal. 1 = Power-down. This bit determines the input levels of the DIRIN pin. DIRIN_PIN 0 = DIRIN accepts input signals down to 200 mV according to AES3 requirements. 1 = DIRIN accepts input signals as defined in the Specifications section. Enables the SYSCLK1 output. SYSCLK1 0 = Enabled. 1 = Disabled. Enables the SYSCLK2 output. SYSCLK2 0 = Enabled. 1 = Disabled. Enables the SYSCLK3 output. SYSCLK3 0 = Enabled. 1 = Disabled. SYSCLK2 1 SYSCLK3 0
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ADAV803
Table 79. ALC Control Register 1
FSSEL1-0 GAINCNTR1-0 RECMODE1-0 LIMDET 7, 6 5, 4 3, 2 1 ADDRESS = 1111011 (0x7B) These bits should equal the sample rate of the ADC. FSSEL1-0 00 = 96 kHz. 01 = 48 kHz. 10 = 32 kHz. 11 = Reserved. These bits determine the limit of the counter used in limited recovery mode. GAINCNTR1-0 00 = 3. 01 = 7. 10 = 15. 11 = 31. These bits determine which recovery mode is used by the ALC section. RECMODE1-0 00 = No recovery. 01 = Normal recovery. 10 = Limited recovery. 11 = Reserved. These bits limit detect mode. LIMDET 0 = ALC is used when either channel exceeds the set limit. 1 = ALC is used only when both channels exceed the set limit. These bits enable ALC. ALCEN 0 = Disable ALC. 1 = Enable ALC. ALCEN 0
Table 80. ALC Control Register 2
RES RECTH1-0 7 6, 5 ADDRESS = 1111100 (0x7C) Recovery threshold. RECTH1-0 00 = -2 dB. 01 = -3 dB. 10 = -4 dB. 11 = -6 dB. Attack threshold. ATKTH1-0 00 = 0 dB. 01 = -1 dB. 10 = -2 dB. 11 = -4 dB. Recovery time selection. RECTIME1-0 00 = 32 ms. 01 = 64 ms. 10 = 128 ms. 11 = 256 ms. Attack timer selection. ATKTIME 0 = 1 ms. 1 = 4 ms. ATKTH1-0 4, 3 RECTIME1-0 2, 1 ATKTIME 0
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ADAV803
Table 81. ALC Control Register 3
ALC RESET 7, 6, 5, 4, 3, 2, 1, 0 ADDRESS = 1111101 (0x7D) A write to this register restarts the ALC operation. The value written to this register is irrelevant. A read from this ALC RESET register gives the gain reduction factor.
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ADAV803 LAYOUT CONSIDERATIONS
Getting the best performance from the ADAV803 requires a careful layout of the printed circuit board (PCB). Using separate analog and digital ground planes is recommended, because these give the currents a low resistance path back to the power supplies. The ground planes should be connected in only one place, usually under the ADAV803, to prevent ground loops. The analog and digital supply pins should be decoupled to their respective ground pins with a 10 F to 47 F tantalum capacitor and a 0.1 F ceramic capacitor. These capacitors should be placed as close as possible to the supply pins. The PLL has its own power supply pins. To get the best performance from the PLL and from the rest of the ADAV803, it is recommended that a separate analog supply be used. Where this is not possible, the user must decide whether to connect the PLL supply to the analog (AVDD) or digital (DVDD) supply. Connecting the PLL supply to AVDD gives the best jitter performance, but can degrade the performance of the ADC and DAC sections slightly due to the increased digital noise created on the AVDD by the PLL. Connecting the PLL supply to DVDD keeps digital noise away from the analog supply, but the jitter specifications might be reduced depending on the quality of the digital supply. Using the layout recommendations described in this section helps to reduce these effects.
ADC
The ADC uses a switch capacitor input stage and is, therefore, particularly sensitive to digital noise. Sources of noise, such as PLLs or clocks, should not be routed close to the ADC section. The CAPxN and CAPxP pins form a charge reservoir for the switched capacitor section of the ADC, so keeping these nodes electrically quiet is a key factor in ensuring good performance. The capacitors connected to these pins should be of good quality, either NPO or COG, and should be placed as close as possible to CAPxN and CAPxP.
RESET AND POWER-DOWN CONSIDERATIONS
When the ADAV803 is held in reset by bringing the RESET pin low, a number of circuit blocks remain powered up. For example, the crystal oscillator circuit based around the XIN and XOUT pins is still active, so that a stable clock source is available when the ADAV803 is taken out of reset. Also, the VCO associated with the SPDIF receiver is active so that the receiver locks to the incoming SPDIF stream in the shortest possible time. Where power consumption is a concern, the individual blocks of the ADAV803 can be powered down via the control registers to gain significant power savings. Table 82 shows typical power savings when using the power-down bits in the control registers. Table 82. Typical Power Requirements
Operating Mode Normal Reset low Power-down bits AVDD (mA) 50 30 12 DVDD (mA) 25 4 0.1 ODVDD (mA) 5 2.5 1.3 DIR_VDD (mA) 5 1 0.7 Power (mW) 280.5 123.75 46.53
DAC
The DAC requires an analog filter to filter out-of-band noise from the analog output. A third-order Bessel filter is recommended, although the filter to use depends on the requirements of the application.
PLL
The PLL can be used to generate digital clocks, either for use internally or to clock external circuitry. Because every clock is a potential source of noise, care should be taken when using the PLL. The ADAV803's PLL outputs can be enabled or disabled, as required. If the PLL clocks are not required by external circuitry, it is recommended that the outputs be disabled. To reduce cross-coupling between clocks, a digital ground trace can be routed on either side of the PLL clock signal, if required.
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ADAV803 OUTLINE DIMENSIONS
0.75 0.60 0.45 1.60 MAX
1
12.00 BSC SQ
64 49 48 PIN 1
SEATING PLANE
TOP VIEW
(PINS DOWN)
10.00 BSC SQ
1.45 1.40 1.35
0.15 0.05
10 6 2
SEATING PLANE
0.20 0.09 7 3.5 0 0.08 MAX COPLANARITY
VIEW A
16 17 32 33
VIEW A
ROTATED 90 CCW
0.50 BSC
0.27 0.22 0.17
COMPLIANT TO JEDEC STANDARDS MS-026BCD
Figure 55. 64-Lead Low Profile Quad Flat Package [LQFP] (ST-64-2) Dimensions shown in millimeters
ORDERING GUIDE
Model ADAV803ASTZT1 ADAV803ASTZ-REEL1
P PT
Temperature Range -40C to +85C -40C to +85C
Control Interface SPI SPI
DAC Outputs Single-Ended Single-Ended
Package Description 64-Lead Low Profile Quad Flat Package [LQFP] 64-Lead Low Profile Quad Flat Package [LQFP]
Package Option ST-64-2 ST-64-2
1
TP PT
Z = Pb free part.
Purchase of licensed IC components of Analog Devices or one of its sublicensed Associated Companies conveys a license for the purchaser under the Philips IC Patent Rights to use these components in an IC system, provided that the system conforms to the IC Standard Specification as defined by Philips.
(c) 2004 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D04756-0-7/04(0)
Rev. 0 | Page 56 of 56

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